Abstract: Provided are a display panel, an integrated chip, and a display device. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving module and a data writing module. The driving module is configured to supply a driving current to the light-emitting element. The data writing module is configured to write a data signal into the driving module. An operating mode of the display panel includes a first mode and a second mode. The brightness of the display panel in the first mode is greater than the brightness of the display panel in the second mode. In the first mode, the data signal corresponding to the light-emitting element is black state voltage G01, and in the second mode, the data signal corresponding to the light-emitting element is black state voltage G02, where G01?G02.

Abstract: Provided are a display panel, a dimming method thereof, and a display device. When the display panel displays a frame of image, a light emission control signal corresponding to a row of sub-pixels in the display panel includes N pulse periods. N is a positive integer. A pulse period includes first level pulses. The first level pulses include a first target level pulse and a first non-target level pulse. The pulse width of the first target level pulse is different from the pulse width of the first non-target level pulse.

Abstract: Display panel, integrated chip and display apparatus are provided. Display panel includes pixel circuit including drive module, bias adjustment module and initialization module, and light emitting element. Drive module configured to provide drive current to light emitting element, and includes drive transistor; bias adjustment module configured to provide bias adjustment signal to first pole or second pole of drive transistor; initialization module configured to provide initialization signal to light emitting element. Operation modes of display panel include first mode and second mode, and brightness level of display panel in first mode greater than that in second mode. Bias adjustment signal Vs1 in first mode and bias adjustment signal Vs2 in second mode satisfies Vs1?Vs2; and/or, initialization signal Vi1 in first mode and initialization signal Vi2 in second mode satisfies Vi1?Vi2. With embodiments of present disclosure, display uniformity of display panel can be improved.

Abstract: A display panel includes: a pixel circuit, and a light-emitting element, that the pixel circuit includes a driving transistor configured to provide a driving current for the light-emitting element; a working process of the pixel circuit includes a data writing stage, in which a gate of the driving transistor receives a data signal, and a bias adjustment stage, in which a source or drain of the driving transistor receives a bias adjustment signal; and the pixel circuit has a frame refresh frequency F1, and a data refresh frequency including a first data refresh frequency F11 and a second data refresh frequency F22, that at least one second data refresh period includes N11 bias adjustment stages, a bias adjustment signal V11 is inputted in a first bias adjustment stage, and a bias adjustment signal Vi is inputted in an i-th bias adjustment stage, where V11?Vi.

Abstract: A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving module, a data writing module, and a bias adjustment module. The driving module includes a driving transistor. The data writing module is configured to provide a data signal for the driving transistor. The bias adjustment module is configured to provide a bias adjustment signal for the driving transistor. A time period of one frame of the display panel includes a non-light-emitting stage and a light-emitting stage. The non-light-emitting stage includes a bias adjustment stage. At least one of a source or a drain of the driving transistor is configured to receive the bias adjustment signal in the bias adjustment stage. An operating state of the pixel circuit includes a first mode and a second mode.

Abstract: A display panel includes a pixel circuit. An operation process of the pixel circuit includes a first data refresh period, a data adjustment stage, and a second data refresh period set in sequence, the data adjustment stage includes a first data adjustment stage. The first data adjustment stage includes T1 first sub-data adjustment stages set in sequence, each first sub-data adjustment stage includes m1 data writing frames and n1 holding frames. The operation process of the pixel circuit further includes a first data refresh frequency F21 and a second data refresh frequency F22, and F21<F22. When the pixel circuit is operated at the first data refresh frequency F21, the first data adjustment stage includes T11 first sub-data adjustment stages set in sequence. When the pixel circuit is operated at the second data refresh frequency F22, the first data adjustment stage includes T21 first sub-data adjustment stages set in sequence. T11>T21.

Abstract: A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving module, and the driving module includes a driving transistor. A time period of one frame of the display panel includes a non-light-emitting stage and a light-emitting stage, and the non-light-emitting stage includes a bias adjustment stage, in which one of a source and a drain of the driving transistor receives a bias adjustment signal. An operating state of the pixel circuit includes a first mode and a second mode, a time length of the non-light-emitting stage in the first mode is L1, and a time length of the non-light-emitting stage in the second mode is L2, where L1>L2. A working process of the display panel in the first mode includes a first frame, and a working process of the display panel in the second mode includes a second frame.

Abstract: A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving module. The driving module includes a driving transistor. A time period of one frame of the display panel includes a non-light-emitting stage and a light-emitting stage. The non-light-emitting stage includes a bias adjustment stage. A source or a drain of the driving transistor is configured to receive a bias adjustment signal in the bias adjustment stage. In response to a frame refresh rate of the display panel being F1, a time length of the non-light-emitting stage is A1, and a time length of the bias adjustment stage is B1. In response to the frame refresh rate of the display panel being F2, the time length of the non-light-emitting stage is A2, and the time length of the bias adjustment stage is B2. F1<F2. B1/A1>B2/A2 or B1>B2.

Abstract: A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving module and a compensation module. The driving module includes a driving transistor, and the compensation module is connected between a gate and a drain of the driving transistor. A time period of one frame of the display panel includes a non-light-emitting stage and a light-emitting stage, and the non-light-emitting stage includes a bias adjustment stage, in which one of a source and the drain of the driving transistor receives a bias adjustment signal. An operating state of the pixel circuit includes a first mode and a second mode, a time length of the non-light-emitting stage in the first mode is L1, and a time length of the non-light-emitting stage in the second mode is L2, where L1>L2.

Abstract: A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving module. The driving module includes a driving transistor. A time period of one frame of the display panel includes a non-light-emitting stage and a light-emitting stage. The non-light-emitting stage includes a bias adjustment stage. A source or a drain of the driving transistor is configured to receive a bias adjustment signal in the bias adjustment stage. An operation state of the pixel circuit includes a first mode and a second mode. A time length of the non-light-emitting stage in the first mode is L1. A time length of the non-light-emitting stage in the second mode is L2. L1>L2. A time length of at least one sub-bias adjustment stage in a first frame is equal to a time length of at least one sub-bias adjustment stage in a second frame.

Abstract: A light-emission driving substrate includes: a substrate; a device layer disposed on the substrate, wherein the device layer comprises a plurality of first signal lines and second signal lines that are disposed in a light-emitting area, and includes a plurality of first connection terminals and second connection terminals that are disposed in a non-light-emitting area, each of the first connection terminals is electrically connected to an anode of the light-emitting element through the first signal line, and each of the second connection terminals is electrically connected to the cathode of a light-emitting element through the second signal line; and wherein a distance between at least one of the first connection terminals and the binding area is smaller than a distance between each of the second connection terminals and the binding area.

Abstract: A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving module, and the driving module includes a driving transistor. A time period of one frame of the display panel includes a non-light-emitting stage and a light-emitting stage, and the non-light-emitting stage includes a bias adjustment stage, in which one of a source and a drain of the driving transistor receives a bias adjustment signal. An operating state of the pixel circuit includes a first mode and a second mode, a time length of the non-light-emitting stage in the first mode is L1, and a time length of the non-light-emitting stage in the second mode is L2, where L1>L2. A working process of the display panel in the first mode includes a first frame, and a working process of the display panel in the second mode includes a second frame.

Abstract: A display panel includes a pixel circuit, a driving circuit, and a clock signal line. The driving circuit is configured to provide a control signal to the pixel circuit. The clock signal line is configured to provide a clock signal for the driving circuit. A data refresh period of the pixel circuit includes a data writing stage and a holding stage, and the holding stage includes N stages arranged in sequence, N?1. When the pixel circuit is operated in the data writing stage, a clock pulse frequency of the clock signal is a first frequency F1. When the pixel circuit is operated in the holding stage, in at least one stage of the N stages, the clock pulse frequency of the clock signal is a second frequency F2, F1>F2>0. The pixel circuit includes a driving transistor, a first transistor, and a second transistor.

Abstract: Embodiments are generally directed to a system and method for adapting executable object to a processing unit. An embodiment of a method to adapt an executable object from a first processing unit to a second processing unit, comprises: adapting the executable object optimized for the first processing unit of a first architecture, to the second processing unit of a second architecture, wherein the second architecture is different from the first architecture, wherein the executable object is adapted to perform on the second processing unit based on a plurality of performance metrics collected while the executable object is performed on the first processing unit and the second processing unit.

Abstract: A display panel includes a pixel circuit, a driving circuit, and a clock signal line. The driving circuit is configured to provide a control signal to the pixel circuit. The clock signal line is configured to provide a clock signal for the driving circuit. A data refresh period of the pixel circuit includes a data writing stage and a holding stage. The holding stage includes N stages arranged in sequence, N?1. When the pixel circuit is operated in the data writing stage, a clock pulse frequency of the clock signal is a first frequency F1. When the pixel circuit is operated in the holding stage, in at least one stage of the N stages, the clock pulse frequency of the clock signal is a second frequency F2.

Abstract: A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving module. The driving module includes a driving transistor, and is configured to provide a driving current for the light-emitting element. The pixel circuit includes a control terminal configured to receive a first light-emitting control signal, the first light-emitting control signal is an effective pulse, and the driving module corresponding to the control terminal is turned on during the effective pulse. A time period of one frame of the display panel includes a non-light-emitting stage and a light-emitting stage, an operating state of the pixel circuit includes a first mode and a second mode, a time length of the non-light-emitting stage in the first mode is L1, and a time length of the non-light-emitting stage in the second mode is L2, where L1>L2.

Abstract: A display panel includes a pixel circuit. An operation process of the pixel circuit includes a first data refresh period, a data adjustment stage, and a second data refresh period set in sequence, the data adjustment stage includes a first data adjustment stage, a second data adjustment stage, and a third data adjustment stage set in sequence. The first data adjustment stage includes T1 first sub-data adjustment stages set in sequence, each first sub-data adjustment stage includes m1 data writing frames and n1 holding frames. The second data adjustment stage includes T2 second sub-data adjustment stages set in sequence, each second sub-data adjustment stage includes m2 data writing frames and n2 holding frames. The third data adjustment stage includes T3 third sub-data adjustment stages set in sequence, each third sub-data adjustment stage includes m3 data writing frames and n3 holding stages set in sequence.

Abstract: A display panel and a display device are provided. The display panel includes a pixel circuit. An operation process of the pixel circuit includes a first data refresh period, a data adjustment stage, and a second data refresh period set in sequence, the data adjustment stage includes a first data adjustment stage and a second data adjustment stage set in sequence. The first data adjustment stage includes T1 first sub-data adjustment stages set in sequence, each first sub-data adjustment stage includes m1 data writing frames and nl holding frames, T1?1, m1?0, n1?0, and m1+n1?1. The second data adjustment stage includes T2 second sub-data adjustment stages set in sequence, each second sub-data adjustment stage includes m2 data writing frames and n2 holding frames, T2?1, m2?0, n2?0, and m2+n2?1. T1>T2, T1/T2=(m2+n2)/(m1+n1).

Abstract: A display panel and a display device are provided. The display panel includes a pixel circuit, a driving circuit configured to provide a control signal for the pixel circuit, and a clock signal line configured to provide a clock signal for the driving circuit. A data refresh period of the pixel circuit includes a data writing stage and a holding stage, the holding stage includes N stage arranged in sequence and N?1. When the pixel circuit is operated in the data writing stage, the clock pulse frequency of the clock signal is a first frequency F1; when the pixel circuit is operated in the holding stage, in at least one of the N stages, the clock pulse frequency of the clock signal is a second frequency F2; and F1>F2>0.

Abstract: A display panel includes: a pixel circuit, and a light-emitting element, that the pixel circuit includes a driving transistor configured to provide a driving current for the light-emitting element; a working process of the pixel circuit includes a data writing stage, in which a gate of the driving transistor receives a data signal, and a bias adjustment stage, in which a source or drain of the driving transistor receives a bias adjustment signal; and the pixel circuit has a frame refresh frequency F1, and a data refresh frequency including a first data refresh frequency F11 and a second data refresh frequency F22, that at least one second data refresh period includes N11 bias adjustment stages, a bias adjustment signal V11 is inputted in a first bias adjustment stage, and a bias adjustment signal Vi is inputted in an i-th bias adjustment stage, where V11?Vi.