Abstract: A display panel includes: a pixel circuit, and a light-emitting element, that the pixel circuit includes a driving transistor configured to provide a driving current for the light-emitting element; a working process of the pixel circuit includes a data writing stage, in which a gate of the driving transistor receives a data signal, and a bias adjustment stage, in which a source or drain of the driving transistor receives a bias adjustment signal; and the pixel circuit has a frame refresh frequency F1, and a data refresh frequency including a first data refresh frequency F11 and a second data refresh frequency F22, that at least one second data refresh period includes N11 bias adjustment stages, a bias adjustment signal V11 is inputted in a first bias adjustment stage, and a bias adjustment signal Vi is inputted in an i-th bias adjustment stage, where V11?Vi.

Abstract: A display panel and a display device are provided. The display panel includes a pixel circuit, a driving circuit configured to provide a control signal for the pixel circuit, and a clock signal line configured to provide a clock signal for the driving circuit. A data refresh period of the pixel circuit includes a data writing stage and a holding stage, the holding stage includes N stage arranged in sequence and N>1. When the pixel circuit is operated in the data writing stage, the clock pulse frequency of the clock signal is a first frequency F1; when the pixel circuit is operated in the holding stage, in at least one of the N stages, the clock pulse frequency of the clock signal is a second frequency F2; and F1>F2>0.

Abstract: A display panel and a display device are provided. The display panel includes a pixel circuit; and a light-emitting element. The operation process of the pixel circuit includes a first data refresh period, a data adjustment stage, and a second data refresh period set in sequence. The data adjustment stage includes T1 first sub-data adjustment stages set in sequence and T2 second sub-data adjustment stages set in sequence. A quantity of the data writing frames in the first sub-data adjustment stage is greater than a quantity of the data writing frames in the second sub-data adjustment stage. A quantity of the holding frames in the first sub-data adjustment stage is smaller than a quantity of the holding frames in the second sub-data adjustment stage.

Abstract: A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving module, and the driving module includes a driving transistor. A time period of one frame of the display panel includes a non-light-emitting stage and a light-emitting stage, and the non-light-emitting stage includes a bias adjustment stage, in which one of a source and a drain of the driving transistor receives a bias adjustment signal. An operating state of the pixel circuit includes a first mode and a second mode, a time length of the non-light-emitting stage in the first mode is L1, and a time length of the non-light-emitting stage in the second mode is L2, where L1>L2. A working process of the display panel in the first mode includes a first frame, and a working process of the display panel in the second mode includes a second frame.

Abstract: Provided are a display panel and a display device. The display panel includes a pixel driver circuit. The pixel driver circuit includes a light-emitting module, a drive transistor and at least one light-emitting control transistor. The drive transistor, the light-emitting control transistor and the light-emitting module are connected in series between a first power supply signal terminal and a second power supply signal terminal, and at least one of the drive transistor or the light-emitting control transistor is a first double-gate transistor. The first double-gate transistor includes a first gate, a second gate and a first source, and the second gate is electrically connected to the first source.

Abstract: A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving module, and the driving module includes a driving transistor. A time period of one frame of the display panel includes a non-light-emitting stage and a light-emitting stage, and the non-light-emitting stage includes a bias adjustment stage, in which one of a source and a drain of the driving transistor receives a bias adjustment signal. An operating state of the pixel circuit includes a first mode and a second mode, a time length of the non-light-emitting stage in the first mode is L1, and a time length of the non-light-emitting stage in the second mode is L2, where L1>L2. A working process of the display panel in the first mode includes a first frame, and a working process of the display panel in the second mode includes a second frame.

Abstract: A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving module. The driving module includes a driving transistor. A time period of one frame of the display panel includes a non-light-emitting stage and a light-emitting stage. The non-light-emitting stage includes a bias adjustment stage. A source or a drain of the driving transistor is configured to receive a bias adjustment signal in the bias adjustment stage. An operation state of the pixel circuit includes a first mode and a second mode. A time length of the non-light-emitting stage in the first mode is L1. A time length of the non-light-emitting stage in the second mode is L2. L1>L2. A time length of at least one sub-bias adjustment stage in a first frame is equal to a time length of at least one sub-bias adjustment stage in a second frame.

Abstract: A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving module and a compensation module. The driving module includes a driving transistor, and the compensation module is connected between a gate and a drain of the driving transistor. A time period of one frame of the display panel includes a non-light-emitting stage and a light-emitting stage, and the non-light-emitting stage includes a bias adjustment stage, in which one of a source and the drain of the driving transistor receives a bias adjustment signal. An operating state of the pixel circuit includes a first mode and a second mode, a time length of the non-light-emitting stage in the first mode is L1, and a time length of the non-light-emitting stage in the second mode is L2, where L1>L2.

Abstract: A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving module. The driving module includes a driving transistor. A time period of one frame of the display panel includes a non-light-emitting stage and a light-emitting stage. The non-light-emitting stage includes a bias adjustment stage. A source or a drain of the driving transistor is configured to receive a bias adjustment signal in the bias adjustment stage. In response to a frame refresh rate of the display panel being F1, a time length of the non-light-emitting stage is A1, and a time length of the bias adjustment stage is B1. In response to the frame refresh rate of the display panel being F2, the time length of the non-light-emitting stage is A2, and the time length of the bias adjustment stage is B2. F1<F2. B1/A1>B2/A2 or B1>B2.

Abstract: A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving module. The driving module includes a driving transistor, and is configured to provide a driving current for the light-emitting element. The pixel circuit includes a control terminal configured to receive a first light-emitting control signal, the first light-emitting control signal is an effective pulse, and the driving module corresponding to the control terminal is turned on during the effective pulse. A time period of one frame of the display panel includes a non-light-emitting stage and a light-emitting stage, an operating state of the pixel circuit includes a first mode and a second mode, a time length of the non-light-emitting stage in the first mode is L1, and a time length of the non-light-emitting stage in the second mode is L2, where L1>L2.

Abstract: Embodiments are generally directed to a system and method for adapting executable object to a processing unit. An embodiment of a method to adapt an executable object from a first processing unit to a second processing unit, comprises: adapting the executable object optimized for the first processing unit of a first architecture, to the second processing unit of a second architecture, wherein the second architecture is different from the first architecture, wherein the executable object is adapted to perform on the second processing unit based on a plurality of performance metrics collected while the executable object is performed on the first processing unit and the second processing unit.

Abstract: The present disclosure provides a display panel, including: a pixel circuit, and a light-emitting element, that the pixel circuit includes a driving transistor configured to provide a driving current for the light-emitting element; a working process of the pixel circuit includes a data writing stage, in which a gate of the driving transistor receives a data signal, and a bias adjustment stage, in which a source or drain of the driving transistor receives a bias adjustment signal; and the pixel circuit has a frame refresh frequency F1, and a data refresh frequency including a first data refresh frequency F11 and a second data refresh frequency F22, that one second data refresh period includes N11 bias adjustment stages, a bias adjustment signal V11 is inputted in a first bias adjustment stage, and a bias adjustment signal Vi is inputted in an i-th bias adjustment stage, where V11?Vi.

Abstract: An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core Timing Control (CTC) signals that are used to control voltages applied in the memory structure. In one aspect, information from which the CTC signals may be generated is pre-computed and stored. This pre-computation may be performed in a power on phase of the memory system. When a request to perform a memory operation is received, the stored information may be accessed and used to generate the CTC signals to control the memory operation. Thus, considerable time and/or power is saved. Note that this time savings occurs each time the memory operation is performed. Also, power is saved due to not having to repeatedly perform the computation.

Abstract: Display panel, integrated chip and display apparatus are provided. Display panel includes pixel circuit including drive module, bias adjustment module and initialization module, and light emitting element. Drive module configured to provide drive current to light emitting element, and includes drive transistor; bias adjustment module configured to provide bias adjustment signal to first pole or second pole of drive transistor; initialization module configured to provide initialization signal to light emitting element. Operation modes of display panel include first mode and second mode, and brightness level of display panel in first mode greater than that in second mode. Bias adjustment signal Vs1 in first mode and bias adjustment signal Vs2 in second mode satisfies Vs1?Vs2; and/or, initialization signal Vi1 in first mode and initialization signal Vi2 in second mode satisfies Vi1?Vi2. With embodiments of present disclosure, display uniformity of display panel can be improved.

Abstract: A display panel and a display device are provided. The display panel includes a pixel circuit including a driving module and a compensation module. The driving module includes a driving transistor, and the compensation module is connected between a gate and a drain of the driving transistor. A time period of one frame includes a non-light-emitting stage including a bias adjustment stage. In the bias adjustment stage, the compensation module is turned off, and one of a source and the drain of the driving transistor receives a bias adjustment signal for adjusting a bias state of the driving transistor. Time lengths of the non-light-emitting stages in the first mode and the second mode are L1 and L2, respectively, where L1>L2. Time lengths of the bias adjustment stages in the first frame in the first mode and the second frame in the second mode are W1 and W2, where W1/L1<W2/L2.

Abstract: Provided are a display panel and a display device. The display panel includes a substrate, a driving circuit layer disposed on the substrate and including driving circuits, LED chips located on side of the drive circuit layer facing away from the substrate and each electrically connected to a corresponding drive circuit, the drive circuit includes at least one first thin film transistor with a source and a drain located at first metal layer of the drive circuit layer and electrically connected to first electrode of corresponding LED chip, and at least part of edges of the display panel is provided with thermally conductive adhesive. The substrate is also provided with one or more layers of thermally conductive metal, at least one layer of thermally conductive metal extends to the edges of the display panel and is in contact with the thermally conductive adhesive.

Abstract: A pixel circuit, a method for driving a pixel circuit and a display panel are provided. An exemplary pixel circuit includes a data writing module and a driving transistor, a voltage of a first terminal of the driving transistor being greater than a voltage of a second terminal; a light-emitting control module and a light-emitting device, the light-emitting device being configured to emit light in response to the driving current generated by the driving transistor; a first initialization module and a second initialization module; and a reset module configured to cause the voltage of the second terminal of the driving transistor to be greater than or equal to the voltage of the first terminal of the driving transistor in response to a current-stage reset signal, an enable signal of the current-stage reset signal appearing after an enable signal of the current-stage light-emitting signal.

Abstract: An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core Timing Control (CTC) signals that are used to control voltages applied in the memory structure. In one aspect, information from which the CTC signals may be generated is pre-computed and stored. This pre-computation may be performed in a power on phase of the memory system. When a request to perform a memory operation is received, the stored information may be accessed and used to generate the CTC signals to control the memory operation. Thus, considerable time and/or power is saved. Note that this time savings occurs each time the memory operation is performed. Also, power is saved due to not having to repeatedly perform the computation.

Abstract: An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core Timing Control (CTC) signals that are used to control voltages applied in the memory structure. In one aspect, information from which the CTC signals may be generated is pre-computed and stored. This pre-computation may be performed in a power on phase of the memory system. When a request to perform a memory operation is received, the stored information may be accessed and used to generate the CTC signals to control the memory operation. Thus, considerable time and/or power is saved. Note that this time savings occurs each time the memory operation is performed. Also, power is saved due to not having to repeatedly perform the computation.

Abstract: A display panel is provided. The display panel includes a display area and a border area. The display area includes multiple display units. The border area includes a drive circuit and at least one pressure detection element. A drive signal is provided by the drive circuit to the display units. The pressure detection element and the drive circuit are arranged in different layers. The pressure detection element is used to detect a pressure signal in the display panel.