Patents by Inventor Yuhong Cai

Yuhong Cai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180366441
    Abstract: An electronic assembly includes a plurality of electronic die arranged into shingles, each shingle having a multiple offset stacked die coupled by cascading connections. Each shingle is arranged in a stack of shingles with alternate shingles having die stacked in opposite directions and offset in a zigzag manner to facilitate vertical electrical connections from a top of the electronic assembly to a bottom die of each shingle.
    Type: Application
    Filed: December 2, 2015
    Publication date: December 20, 2018
    Inventors: Min-Tih Ted Lai, Florence R. Pon, Yuhong Cai, John G. Meyers
  • Patent number: 10051763
    Abstract: Electronic device package technology is disclosed. In one example, an electronic device includes a substrate having at least one electronic component mounted thereon and a heatsink thermally coupled to the electronic component. A plurality of fasteners attaches the heatsink to the substrate. At least one of the substrate, the heatsink, and the plurality of fasteners include a stress-relieving component to minimize fastener stress on the substrate. The stress-relieving component can comprise a fastener having a compliant device (e.g., a spring) for z-direction stress relief. The stress-relieving component can comprise the substrate and/or the heatsink having an oversized aperture for x-direction and/or y-direction stress relief. A method is disclosed for coupling a substrate to a heatsink. A method is disclosed for minimizing fastener stress locally to fasteners of an electronic device.
    Type: Grant
    Filed: October 1, 2016
    Date of Patent: August 14, 2018
    Assignee: Intel Corporation
    Inventors: Yuhong Cai, Min-Thi Lai, Garrick Chow, Lianhua Fan
  • Publication number: 20180098421
    Abstract: Electronic device package technology is disclosed. In one example, an electronic device includes a substrate having at least one electronic component mounted thereon and a heatsink thermally coupled to the electronic component. A plurality of fasteners attaches the heatsink to the substrate. At least one of the substrate, the heatsink, and the plurality of fasteners include a stress-relieving component to minimize fastener stress on the substrate. The stress-relieving component can comprise a fastener having a compliant device (e.g., a spring) for z-direction stress relief. The stress-relieving component can comprise the substrate and/or the heatsink having an oversized aperture for x-direction and/or y-direction stress relief. A method is disclosed for coupling a substrate to a heatsink. A method is disclosed for minimizing fastener stress locally to fasteners of an electronic device.
    Type: Application
    Filed: October 1, 2016
    Publication date: April 5, 2018
    Applicant: Intel Corporation
    Inventors: Yuhong Cai, Min-Thi Lai, Garrick Chow, Lianhua Fan
  • Publication number: 20170186701
    Abstract: Crack resistant electronic device package substrate technology is disclosed. In an example, an electronic device package substrate can include a substrate core material having a surface. The substrate can also include a solder ball pad coupled to the surface of the substrate. In addition, the substrate can include a layer of solder resist material coupled to the surface of the substrate at a location that leaves a gap in between a lateral side of the solder ball pad and the solder resist material.
    Type: Application
    Filed: December 26, 2015
    Publication date: June 29, 2017
    Applicant: Intel Corporation
    Inventors: Yuhong Cai, Sireesha Gogineni, John Yap
  • Publication number: 20040237066
    Abstract: A method of generating a high level design of a distributed system test bed comprising the steps of defining a meta-model of the test bed; defining at least two architecture modelling elements within the meta-model to form an architecture model associated with the meta-model; defining at least one relationship between a pair of architecture modelling elements; defining properties associated with at least one of the architecture modeling elements; and storing the high level design in computer memory.
    Type: Application
    Filed: April 19, 2004
    Publication date: November 25, 2004
    Applicant: Auckland UniServices Limited
    Inventors: John Grundy, John Gordon Hosking, Yuhong Cai