Patents by Inventor Yuichi Matsui

Yuichi Matsui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200357712
    Abstract: An electronic component built-in wiring board includes a substrate having a cavity, an electronic component accommodated in the cavity of the substrate and having pads on a surface of the component, a coating insulating layer formed on the substrate such that the insulating layer is covering the component and has via holes, via conductors formed in the via holes such that the via conductors are penetrating through the insulating layer, and a resin coating formed between the component and the insulating layer and having through holes such that the through holes are partially exposing the pads in the via holes and that the coating has adhesion to the component that is stronger than adhesion of the insulating layer to the component. The via conductors are formed in the via holes and the through holes such that the via conductors are connected to the pads on the surface of the component.
    Type: Application
    Filed: May 8, 2020
    Publication date: November 12, 2020
    Applicant: IBIDEN CO., LTD.
    Inventors: Yusuke TANAKA, Tomohiro Futatsugi, Yuichi Nakamura, Yoshiki Matsui, Keinosuke Ino, Tomohiro Fuwa, Seiji Izawa
  • Publication number: 20200359500
    Abstract: A wiring board for a built-in electronic component includes a first insulating layer, a second insulating layer formed under the first insulating layer, and a conductor layer formed on an upper surface of the second insulating layer such that a cavity is formed to penetrate through the first insulating layer and the conductor layer and expose the second insulating layer at a bottom of the cavity and is formed to accommodate an electronic component therein. The first insulating layer and the conductor layer are formed such that the cavity has a first inner side surface extending from an upper opening edge to a position closer to the second insulating layer, and a lateral expansion part formed between a lower edge of the first inner side surface and the second insulating layer and extending outward from the lower edge of the first inner side surface.
    Type: Application
    Filed: May 11, 2020
    Publication date: November 12, 2020
    Applicant: IBIDEN CO., LTD.
    Inventors: Yusuke TANAKA, Tomohiro FUTATSUGI, Yuichi NAKAMURA, Yoshiki MATSUI
  • Patent number: 10758958
    Abstract: A roller hemming processing device that has first to fifth processing surfaces and that rolls the respective processing surfaces while pressing the respective processing surfaces against a hemming flange in such a posture that an axis of a roller is parallel to an outer panel is used. A pre-processed portion obtained by bending the hemming flange to form a right angle with an inner flange is molded by using the third, fifth and fourth processing surfaces in a stepwise manner such that the angle of inclination with respect to the axis decreases. The pre-processed portion is inclined toward an inner panel side by using the second processing surface. An inclined wall portion that is inclined to contact the inner panel, and a hem portion that is in close contact with the inner panel are molded by simultaneously using the first and second processing surfaces.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: September 1, 2020
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, Takatsu MFG. Co., Ltd.
    Inventors: Jiro Tsukamoto, Tamito Matsui, Yuichi Yamashita, Tsukasa Kume, Kazumoto Suzuki, Atsushi Mizutani
  • Publication number: 20150214476
    Abstract: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.
    Type: Application
    Filed: April 9, 2015
    Publication date: July 30, 2015
    Inventors: Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Naoki Yamamoto, Hideyuki Matsuoka, Tomio Iwasaki
  • Patent number: 8890107
    Abstract: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: November 18, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Naoki Yamamoto, Hideyuki Matsuoka, Tomio Iwasaki
  • Patent number: 8866120
    Abstract: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: October 21, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Naoki Yamamoto, Hideyuki Matsuoka, Tomio Iwasaki
  • Patent number: 8859344
    Abstract: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: October 14, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Naoki Yamamoto, Hideyuki Matsuoka, Tomio Iwasaki
  • Patent number: 8833857
    Abstract: A vehicle seat includes a pair of lower rails that are attached to a vehicle floor and extend parallel to one another, a pair of upper rails that are slidably attached to the lower rails, and a seat cushion that is attached to the pair of upper rails. The seat cushion includes i) a pair of pipe members, each pipe member being a single member that includes a long portion that extends along the corresponding upper rail, and a leg portion that extends downward from a first end portion of the long portion and that is attached to the corresponding upper rail; ii) a first connecting pipe that connects the first end portions of the pair of long portions together; and iii) a pair of plate members extending from the upper rails to the long portions, and attached to second end portions of the long portions.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: September 16, 2014
    Assignee: Toyota Boshoku Kabushiki Kaisha
    Inventors: Yoshiro Hara, Yuichi Matsui, Yukinori Sugiura, Tatsuya Ono, Takashi Okada
  • Patent number: 8618523
    Abstract: On an insulating film (41) in which a plug (43) as a lower electrode is embedded, a laminated layer pattern of an insulating film (51) made of tantalum oxide, a recording layer (52) made of Ge—Sb—Te based chalcogenide to which indium is introduced and an upper electrode film (53) made of tungsten or tungsten alloy is formed, thereby forming a phase change memory. By interposing the insulating film (51) between the recording layer (52) and the plug (43), an effect of reducing programming current of a phase change memory and an effect of preventing peeling of the recording layer (52) can be achieved. Further, by using the Ge—Sb—Te based chalcogenide to which indium is introduced as the recording layer (52), the difference in work function between the insulating film (51) and the recording layer (52) is increased, and the programming voltage of the phase change memory can be reduced.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: December 31, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Norikatsu Takaura, Yuichi Matsui, Motoyasu Terao, Yoshihisa Fujisaki, Nozomu Matsuzaki, Kenzo Kurotsuchi, Takahiro Morikawa
  • Publication number: 20120241715
    Abstract: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.
    Type: Application
    Filed: June 11, 2012
    Publication date: September 27, 2012
    Inventors: YUICHI MATSUI, Nozomu Matsuzaki, Norikatsu Takaura, Naoki Yamamoto, Hideyuki Matsuoka, Tomio Iwasaki
  • Publication number: 20120077325
    Abstract: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.
    Type: Application
    Filed: December 7, 2011
    Publication date: March 29, 2012
    Inventors: YUICHI MATSUI, Nozomu Matsuzaki, Norikatsu Takaura, Naoki Yamamoto, Hideyuki Matsuoka, Tomio Iwasaki
  • Publication number: 20120074377
    Abstract: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.
    Type: Application
    Filed: December 7, 2011
    Publication date: March 29, 2012
    Inventors: YUICHI MATSUI, Nozomu MATSUZAKI, Norikatsu TAKAURA, Naoki YAMAMOTO, Hideyuki MATSUOKA, Tomio IWASAKI
  • Publication number: 20120025579
    Abstract: A vehicle seat includes a back frame including: a back frame body that is formed by bending a pipe into a rectangular form such that both ends of the pipe are located at one of four corner portions of the rectangular form; and a pair of side frames that are joined, respectively, to a first corner portion which is one of the corner portions of the back frame body and at which the both ends of the pipe are located and a second corner portion that is another of the corner portions of the back frame body and is laterally next to the first corner portion. One of the ends of the pipe is butt-welded to one of the side frames.
    Type: Application
    Filed: July 21, 2011
    Publication date: February 2, 2012
    Applicant: TOYOTA BOSHOKU KABUSHIKI KAISHA
    Inventors: Tatsuya ONO, Yuichi MATSUI, Yukinori SUGIURA, Yoshiro HARA, Takashi OKADA
  • Patent number: 8106441
    Abstract: A memory cell capacitor (C3) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M3) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: January 31, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Satoru Akiyama, Takao Watanabe, Yuichi Matsui, Masahiko Hiratani
  • Publication number: 20120019039
    Abstract: A vehicle seat includes a pair of lower rails that are attached to a vehicle floor and extend parallel to one another, a pair of upper rails that are slidably attached to the lower rails, and a seat cushion that is attached to the pair of upper rails. The seat cushion includes i) a pair of pipe members, each pipe member being a single member that includes a long portion that extends along the corresponding upper rail, and a leg portion that extends downward from a first end portion of the long portion and that is attached to the corresponding upper rail; ii) a first connecting pipe that connects the first end portions of the pair of long portions together; and iii) a pair of plate members extending from the upper rails to the long portions, and attached to second end portions of the long portions.
    Type: Application
    Filed: July 19, 2011
    Publication date: January 26, 2012
    Applicant: TOYOTA BOSHOKU KABUSHIKI KAISHA
    Inventors: Yoshiro HARA, Yuichi MATSUI, Yukinori SUGIURA, Tatsuya ONO, Takashi OKADA
  • Patent number: 8044489
    Abstract: A semiconductor device having a phase-change memory cell comprises an interlayer dielectric film formed of, for example, SiOF formed on a select transistor formed on a main surface of a semiconductor substrate, a chalcogenide material layer formed of, for example, GeSbTe extending on the interlayer dielectric film, and a top electrode formed on the chalcogenide material layer. A fluorine concentration in an interface between the interlayer dielectric film and the chalcogenide material layer is higher than a fluorine concentration in an interface between the chalcogenide material layer and the top electrode.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: October 25, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Yuichi Matsui
  • Publication number: 20110215288
    Abstract: Since a chalcogenide material has low adhesion to a silicon oxide film, there is a problem in that it tends to separate from the film during the manufacturing step of a phase change memory. In addition, since the chalcogenide material has to be heated to its melting point or higher during resetting (amorphization) of the phase change memory, there is a problem of requiring extremely large rewriting current. An interfacial layer includes an extremely thin insulator or semiconductor having the function as both an adhesive layer and a high resistance layer (thermal resistance layer) is inserted between chalcogenide material layer/interlayer insulative film and between chalcogenide material layer/plug.
    Type: Application
    Filed: May 16, 2011
    Publication date: September 8, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuichi MATSUI, Tomio IWASAKI, Norikatsu TAKAURA, Kenzo KUROTSUCHI
  • Patent number: 8000126
    Abstract: A phase change memory is formed of a plug buried within a through-hole in an insulating film formed on a semiconductor substrate, an interface layer formed on the insulating film in which the plug is buried, a recording layer formed of a chalcogenide layer formed on the interface layer, and an upper contact electrode formed on the recording layer. The recording layer storing information according to resistance value change is made of chalcogenide material containing indium in an amount range from 20 atomic % to 38 atomic %, germanium in a range from 9 atomic % to 28 atomic %, antimony in a range from 3 atomic % to 18 atomic %, and tellurium in a range from 42 atomic % to 63 atomic %, where the content of germanium larger than or equal to the content of antimony.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: August 16, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Takahiro Morikawa, Motoyasu Terao, Norikatsu Takaura, Kenzo Kurotsuchi, Nozomu Matsuzaki, Yoshihisa Fujisaki, Masaharu Kinoshita, Yuichi Matsui
  • Publication number: 20110049454
    Abstract: In a phase-change memory, an interface layer is inserted between a chalcogenide material layer and a plug. The interface layer is arranged so as not to cover the entire interface of a plug-like electrode. When the plug is formed at an upper part than the chalcogenide layer, the degree of integration is increased. The interface layer is formed by carrying out sputtering using an oxide target, or, by forming a metal film by carrying out sputtering using a metal target followed by oxidizing the metal film in an oxidation atmosphere such as oxygen radical, oxygen plasma, etc.
    Type: Application
    Filed: June 23, 2006
    Publication date: March 3, 2011
    Inventors: Motoyasu Terao, Yuichi Matsui, Tsuyoshi Koga, Nozomu Matsuzaki, Norikatsu Takaura, Yoshihisa Fujisaki, Kenzo Kurotsuchi, Takahiro Morikawa, Yoshitaka Sasago, Junko Ushiyama, Akemi Hirotsune
  • Publication number: 20100314676
    Abstract: A memory cell capacitor (C3) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M3) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs.
    Type: Application
    Filed: August 23, 2010
    Publication date: December 16, 2010
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Satoru Akiyama, Takao Watanabe, Yuichi Matsui, Masahiko Hiratani