Patents by Inventor Yuichi Minoura

Yuichi Minoura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230231045
    Abstract: A semiconductor device includes a channel layer configured to include a first nitride semiconductor containing gallium (Ga) and a first crystal dislocation density, and a barrier layer provided over a first surface side of the channel layer, and configured to include a second nitride semiconductor containing aluminum (Al) and a second crystal dislocation density, wherein the second crystal dislocation density is larger than the first crystal dislocation density.
    Type: Application
    Filed: October 24, 2022
    Publication date: July 20, 2023
    Applicant: Fujitsu Limited
    Inventors: Atsushi YAMADA, Yuichi MINOURA, Yusuke KUMAZAKI
  • Patent number: 10964805
    Abstract: A compound semiconductor device includes a compound semiconductor laminate structure including an electron transit layer and an electron supply layer, a gate electrode, a source electrode, and a drain electrode that are formed over the electron supply layer, a first insulating layer of diamond formed between the gate electrode and the drain electrode over the compound semiconductor laminate structure, and a second insulating layer formed between the gate electrode and the source electrode over the compound semiconductor laminate structure, wherein a positive compressive stress is applied from the first insulating layer to the electron supply layer, and a compressive stress from the second insulating layer to the electron supply layer is smaller than the compressive stress from the first insulating layer to the electron supply layer.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: March 30, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Kozo Makiyama, Yuichi Minoura, Yusuke Kumazaki, Toshihiro Ohki, Naoya Okamoto
  • Patent number: 10804358
    Abstract: A compound semiconductor device includes: a compound semiconductor area in which a compound semiconductor plug is embedded and formed; and an ohmic electrode provided on the compound semiconductor plug, wherein the compound semiconductor plug includes, in a side surface portion that is as an interface with the compound semiconductor area, a high concentration dopant layer containing a dopant whose concentration is higher than that of other portions.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: October 13, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Kozo Makiyama, Yuichi Minoura
  • Publication number: 20200058783
    Abstract: A compound semiconductor device includes a compound semiconductor laminate structure including an electron transit layer and an electron supply layer, a gate electrode, a source electrode, and a drain electrode that are formed over the electron supply layer, a first insulating layer of diamond formed between the gate electrode and the drain electrode over the compound semiconductor laminate structure, and a second insulating layer formed between the gate electrode and the source electrode over the compound semiconductor laminate structure, wherein a positive compressive stress is applied from the first insulating layer to the electron supply layer, and a compressive stress from the second insulating layer to the electron supply layer is smaller than the compressive stress from the first insulating layer to the electron supply layer.
    Type: Application
    Filed: August 2, 2019
    Publication date: February 20, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Shirou OZAKI, Kozo Makiyama, Yuichi Minoura, Yusuke Kumazaki, Toshihiro Ohki, NAOYA OKAMOTO
  • Patent number: 10483185
    Abstract: A semiconductor device includes a semiconductor chip including a substrate and an element region on the substrate, a heat transfer body made of diamond, and a metal layer between the semiconductor chip and the heat transfer body, wherein the substrate includes an amorphous region on a back surface thereof, the amorphous region and the metal layer are bonded to each other, and the metal layer and the heat transfer body are bonded to each other.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: November 19, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Yuichi Minoura, Naoya Okamoto, Toshihiro Ohki
  • Publication number: 20190326404
    Abstract: A semiconductor device includes a substrate, a first semiconductor layer formed over the substrate, the first semiconductor layer being composed of a nitride semiconductor, a second semiconductor layer formed over the first semiconductor layer, the second semiconductor layer being composed of a nitride semiconductor and a gate electrode, a source electrode, and a drain electrode that are formed over the second semiconductor layer, wherein the source electrode including a plurality of protrusions that penetrate into the second semiconductor layer, and the protrusions having a side surface inclined with respect to a surface of the first semiconductor layer.
    Type: Application
    Filed: April 8, 2019
    Publication date: October 24, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Yusuke Kumazaki, Toshihiro Ohki, Kozo Makiyama, Shirou OZAKI, Yuichi Minoura
  • Publication number: 20190189746
    Abstract: A compound semiconductor device includes: a compound semiconductor area in which a compound semiconductor plug is embedded and formed; and an ohmic electrode provided on the compound semiconductor plug, wherein the compound semiconductor plug includes, in a side surface portion that is as an interface with the compound semiconductor area, a high concentration dopant layer containing a dopant whose concentration is higher than that of other portions.
    Type: Application
    Filed: November 16, 2018
    Publication date: June 20, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Kozo Makiyama, Yuichi Minoura
  • Publication number: 20190051579
    Abstract: A semiconductor device includes a semiconductor chip including a substrate and an element region on the substrate, a heat transfer body made of diamond, and a metal layer between the semiconductor chip and the heat transfer body, wherein the substrate includes an amorphous region on a back surface thereof, the amorphous region and the metal layer are bonded to each other, and the metal layer and the heat transfer body are bonded to each other.
    Type: Application
    Filed: July 24, 2018
    Publication date: February 14, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Yuichi Minoura, Naoya Okamoto, Toshihiro Ohki
  • Patent number: 9947781
    Abstract: A semiconductor device includes a first semiconductor layer formed of a nitride semiconductor on a substrate, a second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer, a gate trench formed in the second semiconductor layer or in the second and first semiconductor layers, a gate electrode formed at the gate trench, and a source electrode and a drain electrode formed on the second semiconductor layer. The gate trench has terminal parts of a bottom of the gate trench formed shallower than a center part of the bottom. A part of a sidewall of the gate trench is formed of a surface including an a-plane. The center part of the bottom is a c-plane. The terminal parts of the bottom form a slope from the c-plane to the a-plane.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: April 17, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Yuichi Minoura, Naoya Okamoto
  • Publication number: 20170309737
    Abstract: A semiconductor device includes a first semiconductor layer formed of a nitride semiconductor on a substrate, a second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer, a gate trench formed in the second semiconductor layer or in the second and first semiconductor layers, a gate electrode formed at the gate trench, and a source electrode and a drain electrode formed on the second semiconductor layer. The gate trench has terminal parts of a bottom of the gate trench formed shallower than a center part of the bottom. A part of a sidewall of the gate trench is formed of a surface including an a-plane. The center part of the bottom is a c-plane. The terminal parts of the bottom form a slope from the c-plane to the a-plane.
    Type: Application
    Filed: June 29, 2017
    Publication date: October 26, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Yuichi Minoura, Naoya Okamoto
  • Patent number: 9728618
    Abstract: A semiconductor device includes a first semiconductor layer formed of a nitride semiconductor on a substrate, a second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer, a gate trench formed in the second semiconductor layer or in the second and first semiconductor layers, a gate electrode formed at the gate trench, and a source electrode and a drain electrode formed on the second semiconductor layer. The gate trench has terminal parts of a bottom of the gate trench formed shallower than a center part of the bottom. A part of a sidewall of the gate trench is formed of a surface including an a-plane. The center part of the bottom is a c-plane. The terminal parts of the bottom form a slope from the c-plane to the a-plane.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: August 8, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Yuichi Minoura, Naoya Okamoto
  • Patent number: 9685338
    Abstract: A compound semiconductor device includes: a compound semiconductor layered structure; a gate electrode formed above the compound semiconductor layered structure; a first protective insulating film that covers a surface of the compound semiconductor layered structure and is made of silicon nitride as a material; a second protective insulating film that covers the gate electrode on the first protective insulating film and is made of silicon oxide as a material; and a third protective insulating film that contains silicon oxynitride and is formed between the first protective insulating film and the second protective insulating film.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: June 20, 2017
    Assignee: Transphorm Japan, Inc.
    Inventors: Yuichi Minoura, Yoshitaka Watanabe
  • Publication number: 20170125570
    Abstract: A compound semiconductor device includes a compound semiconductor layer including an electron transit layer and an electron supply layer above the electron transit layer, the electron supply layer including a first layer including InAlN and a second layer including InAlGaN formed above the first layer.
    Type: Application
    Filed: October 24, 2016
    Publication date: May 4, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Kozo Makiyama, Yuichi Minoura, Shirou OZAKI
  • Patent number: 9553152
    Abstract: A semiconductor device includes: a first semiconductor layer which is formed over a substrate and is formed from a nitride semiconductor; a second semiconductor layer which is formed over the first semiconductor layer and is formed from a nitride semiconductor; a third semiconductor layer which is formed over the second semiconductor layer and is formed from a nitride semiconductor; a source electrode and a drain electrode which are formed over the third semiconductor layer; an opening which is formed in the second semiconductor layer and the third semiconductor layer between the source electrode and the drain electrode; an insulating layer which is formed on a side surface and a bottom surface of the opening; and a gate electrode which is formed in the opening through the insulating layer.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: January 24, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Toshihiro Ohki, Lei Zhu, Naoya Okamoto, Yuichi Minoura, Shirou Ozaki
  • Publication number: 20160359033
    Abstract: A compound semiconductor device includes: a compound semiconductor layered structure; a gate electrode formed above the compound semiconductor layered structure; a first protective insulating film that covers a surface of the compound semiconductor layered structure and is made of silicon nitride as a material; a second protective insulating film that covers the gate electrode on the first protective insulating film and is made of silicon oxide as a material; and a third protective insulating film that contains silicon oxynitride and is formed between the first protective insulating film and the second protective insulating film.
    Type: Application
    Filed: August 19, 2016
    Publication date: December 8, 2016
    Inventors: Yuichi Minoura, Yoshitaka Watanabe
  • Patent number: 9496380
    Abstract: At least one kind of impurity selected from, for example, Fe, C, B, Ti, Cr is introduced into at least a buffer layer of a compound semiconductor layered structure from a rear surface of the compound semiconductor layered structure to make a resistance value of the buffer layer high.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: November 15, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Yuichi Minoura, Toshihide Kikkawa, Toshihiro Ohki
  • Patent number: 9425268
    Abstract: A compound semiconductor device includes: a compound semiconductor layered structure; a gate electrode formed above the compound semiconductor layered structure; a first protective insulating film that covers a surface of the compound semiconductor layered structure and is made of silicon nitride as a material; a second protective insulating film that covers the gate electrode on the first protective insulating film and is made of silicon oxide as a material; and a third protective insulating film that contains silicon oxynitride and is formed between the first protective insulating film and the second protective insulating film.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: August 23, 2016
    Assignee: Transphorm Japan, Inc.
    Inventors: Yuichi Minoura, Yoshitaka Watanabe
  • Publication number: 20160204241
    Abstract: A semiconductor device includes a first semiconductor layer formed of a nitride semiconductor on a substrate, a second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer, a gate trench formed in the second semiconductor layer or in the second and first semiconductor layers, a gate electrode formed at the gate trench, and a source electrode and a drain electrode formed on the second semiconductor layer. The gate trench has terminal parts of a bottom of the gate trench formed shallower than a center part of the bottom. A part of a sidewall of the gate trench is formed of a surface including an a-plane. The center part of the bottom is a c-plane. The terminal parts of the bottom form a slope from the c-plane to the a-plane.
    Type: Application
    Filed: March 2, 2016
    Publication date: July 14, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Yuichi Minoura, Naoya Okamoto
  • Patent number: 9312350
    Abstract: A semiconductor device includes a first semiconductor layer formed of a nitride semiconductor on a substrate, a second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer, a gate trench formed in the second semiconductor layer or in the second and first semiconductor layers, a gate electrode formed at the gate trench, and a source electrode and a drain electrode formed on the second semiconductor layer. The gate trench has terminal parts of a bottom of the gate trench formed shallower than a center part of the bottom. A part of a sidewall of the gate trench is formed of a surface including an a-plane. The center part of the bottom is a c-plane. The terminal parts of the bottom form a slope from the c-plane to the a-plane.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: April 12, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Yuichi Minoura, Naoya Okamoto
  • Patent number: 9306031
    Abstract: A compound semiconductor device includes a substrate having an opening formed from the rear side thereof; a compound semiconductor layer disposed over the surface of the substrate; a local p-type region in the compound semiconductor layer, partially exposed at the end of the substrate opening; and a rear electrode made of a conductive material, disposed in the substrate opening so as to be connected to the local p-type region.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: April 5, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Yuichi Minoura