Patents by Inventor Yuichi Morinaga

Yuichi Morinaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9583455
    Abstract: Reliability of a semiconductor device is improved. A semiconductor device has a base material of insulating material having a through hole, a terminal formed on a lower surface of the base material, and a semiconductor chip mounted on an upper surface of the base material in a face-up manner. The semiconductor device has a conductive member such as a wire, which electrically connects a pad of the semiconductor chip with an exposed surface of the terminal which is exposed from the through hole of the base material, and has a sealing body for sealing the conductive member, inside of the through hole of the base material, and the semiconductor chip. An anchor is provided in a region of the exposed surface of the terminal which is exposed from the through hole of the base material except for a joint portion joined with the conductive member.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: February 28, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Kenji Oyachi, Tamaki Wada, Yuichi Morinaga
  • Publication number: 20160293564
    Abstract: Reliability of a semiconductor device is improved. A semiconductor device has a base material of insulating material having a through hole, a terminal formed on a lower surface of the base material, and a semiconductor chip mounted on an upper surface of the base material in a face-up manner. The semiconductor device has a conductive member such as a wire, which electrically connects a pad of the semiconductor chip with an exposed surface of the terminal which is exposed from the through hole of the base material, and has a sealing body for sealing the conductive member, inside of the through hole of the base material, and the semiconductor chip. An anchor is provided in a region of the exposed surface of the terminal which is exposed from the through hole of the base material except for a joint portion joined with the conductive member.
    Type: Application
    Filed: April 7, 2016
    Publication date: October 6, 2016
    Applicant: Renesas Electronics Corporation
    Inventors: Kenji OYACHI, Tamaki WADA, Yuichi MORINAGA
  • Patent number: 9337134
    Abstract: Reliability of a semiconductor device is improved. A semiconductor device has a base material comprised of insulating material having a through hole, a terminal formed on a lower surface of the base material, and a semiconductor chip mounted on an upper surface of the base material in a face-up manner. Further, the semiconductor device has a conductive member such as a wire, which electrically connects a pad of the semiconductor chip with an exposed surface of the terminal which is exposed from the through hole of the base material, and has a sealing body for sealing the conductive member, inside of the through hole of the base material, and the semiconductor chip. An anchor means is provided in a region of the exposed surface of the terminal which is exposed from the through hole of the base material except for a joint portion joined with the conductive member such as the wire.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: May 10, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Kenji Oyachi, Tamaki Wada, Yuichi Morinaga
  • Patent number: 9006036
    Abstract: To provide a semiconductor device having an improved quality. The semiconductor device of the invention has a tape substrate having a semiconductor chip thereon, a plurality of land pads placed around the semiconductor chip, a plurality of wires for electrically coupling the electrode pad of the semiconductor chip to the land pad, and a plurality of terminal portions provided on the lower surface of the tape substrate. An average distance between local peaks of the surface roughness of a first region between the land pad of the tape substrate and the semiconductor chip is smaller than an average distance of local peaks of the surface roughness of a second region between the land pad of the tape substrate and the first region.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: April 14, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Tomoko Higashino, Yuichi Morinaga, Kazuya Tsuboi, Tamaki Wada
  • Publication number: 20140353822
    Abstract: Reliability of a semiconductor device is improved. A semiconductor device has a base material comprised of insulating material having a through hole, a terminal formed on a lower surface of the base material, and a semiconductor chip mounted on an upper surface of the base material in a face-up manner. Further, the semiconductor device has a conductive member such as a wire, which electrically connects a pad of the semiconductor chip with an exposed surface of the terminal which is exposed from the through hole of the base material, and has a sealing body for sealing the conductive member, inside of the through hole of the base material, and the semiconductor chip. An anchor means is provided in a region of the exposed surface of the terminal which is exposed from the through hole of the base material except for a joint portion joined with the conductive member such as the wire.
    Type: Application
    Filed: May 15, 2014
    Publication date: December 4, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Kenji OYACHI, Tamaki WADA, Yuichi MORINAGA
  • Publication number: 20140080260
    Abstract: To provide a semiconductor device having an improved quality. The semiconductor device of the invention has a tape substrate having a semiconductor chip thereon, a plurality of land pads placed around the semiconductor chip, a plurality of wires for electrically coupling the electrode pad of the semiconductor chip to the land pad, and a plurality of terminal portions provided on the lower surface of the tape substrate. An average distance between local peaks of the surface roughness of a first region between the land pad of the tape substrate and the semiconductor chip is smaller than an average distance of local peaks of the surface roughness of a second region between the land pad of the tape substrate and the first region.
    Type: Application
    Filed: September 18, 2013
    Publication date: March 20, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Tomoko HIGASHINO, Yuichi MORINAGA, Kazuya TSUBOI, Tamaki WADA
  • Patent number: 7704790
    Abstract: Plural inlets 1 are formed by a separation into individual pieces, and these plural inlets are arranged to a tape-like carrier such that the long side of each of the plural inlets is along the longitudinal direction of the tape-like carrier, whereby cost can be reduced by rearranging the inlets to the cheap tape-like carrier. Further, the plural inlets formed by separating into individual pieces are rearranged onto the tape-like carrier, whereby the change of the arrangement pitch of the inlets so as to correspond to the size of a final product at a customer side can be facilitated, and days taken for the development for newly supplying the inlets can be shortened.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: April 27, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Yuichi Morinaga, Hisao Yamagata, Toru Makanae
  • Patent number: 7663209
    Abstract: Provided are an inlet for an electronic tag comprising an insulating film, antennas each made of a conductor layer and formed over one surface of the insulating film, a slit formed in a portion of each of the antennas and having one end extending toward the outer edge of the antenna, a semiconductor chip electrically connected with each of the antennas via a plurality of bump electrodes, and a resin for sealing the semiconductor chip therewith; and a manufacturing process of the inlet. By the present invention, formation of a thin and highly-reliable inlet for a non-contact type electronic tag can be actualized.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: February 16, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Michio Okamoto, Yuichi Morinaga, Yuji Ikeda, Takeshi Saito
  • Publication number: 20100005647
    Abstract: In order to offer the technology which can form the pattern of the antenna of the inlet for electronic tags accurately and cheaply, the resist layer at the time of forming the pattern of an antenna by chemical etching is formed using a photogravure printing machine. Let the extending direction of region 16C which has the minimum width in the height of the front surface of a gravure plate be an opposite direction to the direction of rotation of a gravure plate (a doctor's relative direction of movement seen from the gravure plate). The radius of curvature of an inner circumference of the curved part in region 16B is made larger than the radius of curvature of a periphery. The outer edge of region 16D is formed so that it may become forward tapered shape-like toward position D, so that the width of region 16D may become larger than the width of region 16C in position D which the end of height attains.
    Type: Application
    Filed: September 14, 2009
    Publication date: January 14, 2010
    Applicant: Renesas Technology Corp.
    Inventors: Yuichi MORINAGA, Yuji IKEDA, Shintaro SAKAMOTO
  • Publication number: 20070193020
    Abstract: In order to offer the technology which can form the pattern of the antenna of the inlet for electronic tags accurately and cheaply, the resist layer at the time of forming the pattern of an antenna by chemical etching is formed using a photogravure printing machine. Let the extending direction of region 16C which has the minimum width in the height of the front surface of a gravure plate be an opposite direction to the direction of rotation of a gravure plate (a doctor's relative direction of movement seen from the gravure plate). The radius of curvature of an inner circumference of the curved part in region 16B is made larger than the radius of curvature of a periphery. The outer edge of region 16D is formed so that it may become forward tapered shape-like toward position D, so that the width of region 16D may become larger than the width of region 16C in position D which the end of height attains.
    Type: Application
    Filed: January 17, 2005
    Publication date: August 23, 2007
    Inventors: Yuichi Morinaga, Yuji Ikeda, Shintaro Sakamoto
  • Publication number: 20060283467
    Abstract: Plural inlets 1 are formed by a separation into individual pieces, and these plural inlets are arranged to a tape-like carrier such that the long side of each of the plural inlets is along the longitudinal direction of the tape-like carrier, whereby cost can be reduced by rearranging the inlets to the cheap tape-like carrier. Further, the plural inlets formed by separating into individual pieces are rearranged onto the tape-like carrier, whereby the change of the arrangement pitch of the inlets so as to correspond to the size of a final product at a customer side can be facilitated, and days taken for the development for newly supplying the inlets can be shortened.
    Type: Application
    Filed: June 16, 2006
    Publication date: December 21, 2006
    Inventors: Yuichi Morinaga, Hisao Yamagata, Toru Makanae
  • Publication number: 20060232415
    Abstract: Provided are an inlet for an electronic tag comprising an insulating film, antennas each made of a conductor layer and formed over one surface of the insulating film, a slit formed in a portion of each of the antennas and having one end extending toward the outer edge of the antenna, a semiconductor chip electrically connected with each of the antennas via a plurality of bump electrodes, and a resin for sealing the semiconductor chip therewith; and a manufacturing process of the inlet. By the present invention, formation of a thin and highly-reliable inlet for a non-contact type electronic tag can be actualized.
    Type: Application
    Filed: June 16, 2006
    Publication date: October 19, 2006
    Inventors: Michio Okamoto, Yuichi Morinaga, Yuji Ikeda, Takeshi Saito
  • Patent number: 7105916
    Abstract: Provided are an inlet for an electronic tag comprising an insulating film, antennas each made of a conductor layer and formed over one surface of the insulating film, a slit formed in a portion of each of the antennas and having one end extending toward the outer edge of the antenna, a semiconductor chip electrically connected with each of the antennas via a plurality of bump electrodes, and a resin for sealing the semiconductor chip therewith; and a manufacturing process of the inlet. By the present invention, formation of a thin and highly-reliable inlet for a non-contact type electronic tag can be actualized.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: September 12, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Michio Okamoto, Yuichi Morinaga, Yuji Ikeda, Takeshi Saito
  • Patent number: 7030763
    Abstract: In the event of the shipment of electronic tags from a manufacturer to a customer, a number of the electronic tags required by the customer are adhered to a double-faced adhesive tape and then the double-faced adhesive tape is wound on a reel. Then, this reel is contained in a case and shipped to the customer. The electronic tag is adhered to an article in the following manner. That is, the double-faced adhesive tape is cut to obtain pieces of the electronic tags, and the cover tape on the rear surface of the double-faced adhesive tape is peeled, and then, the electronic tag is adhered to the article by the use of the double-faced adhesive tape.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: April 18, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Michio Okamoto, Yuichi Morinaga, Yuji Ikeda, Takeshi Saito
  • Patent number: 6762682
    Abstract: In the event of the shipment of electronic tags from a manufacturer to a customer, a number of the electronic tags required by the customer are adhered to a double-faced adhesive tape and then the double-faced adhesive tape is wound on a reel. Then, this reel is contained in a case and shipped to the customer. The electronic tag is adhered to an article in the following manner. That is, the double-faced adhesive tape is cut to obtain pieces of the electronic tags, and the cover tape on the rear surface of the double-faced adhesive tape is peeled, and then, the electronic tag is adhered to the article by the use of the double-faced adhesive tape.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: July 13, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Michio Okamoto, Yuichi Morinaga, Yuji Ikeda, Takeshi Saito
  • Publication number: 20040041262
    Abstract: Provided are an inlet for an electronic tag comprising an insulating film, antennas each made of a conductor layer and formed over one surface of the insulating film, a slit formed in a portion of each of the antennas and having one end extending toward the outer edge of the antenna, a semiconductor chip electrically connected with each of the antennas via a plurality of bump electrodes, and a resin for sealing the semiconductor chip therewith; and a manufacturing process of the inlet. By the present invention, formation of a thin and highly-reliable inlet for a non-contact type electronic tag can be actualized.
    Type: Application
    Filed: August 6, 2003
    Publication date: March 4, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Michio Okamoto, Yuichi Morinaga, Yuji Ikeda, Takeshi Saito
  • Publication number: 20030107486
    Abstract: In the event of the shipment of electronic tags from a manufacturer to a customer, a number of the electronic tags required by the customer are adhered to a double-faced adhesive tape and then the double-faced adhesive tape is wound on a reel. Then, this reel is contained in a case and shipped to the customer. The electronic tag is adhered to an article in the following manner. That is, the double-faced adhesive tape is cut to obtain pieces of the electronic tags, and the cover tape on the rear surface of the double-faced adhesive tape is peeled, and then, the electronic tag is adhered to the article by the use of the double-faced adhesive tape.
    Type: Application
    Filed: January 14, 2003
    Publication date: June 12, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Michio Okamoto, Yuichi Morinaga, Yuji Ikeda, Takeshi Saito
  • Publication number: 20030063002
    Abstract: In the event of the shipment of electronic tags from a manufacturer to a customer, a number of the electronic tags required by the customer are adhered to a double-faced adhesive tape and then the double-faced adhesive tape is wound on a reel. Then, this reel is contained in a case and shipped to the customer. The electronic tag is adhered to an article in the following manner. That is, the double-faced adhesive tape is cut to obtain pieces of the electronic tags, and the cover tape on the rear surface of the double-faced adhesive tape is peeled, and then, the electronic tag is adhered to the article by the use of the double-faced adhesive tape.
    Type: Application
    Filed: September 27, 2002
    Publication date: April 3, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Michio Okamoto, Yuichi Morinaga, Yuji Ikeda, Takeshi Saito
  • Patent number: 6518655
    Abstract: A multi-chip package type semiconductor device includes a first insulating substrate having a hollow on its main surface, a second insulating substrate having on its main surface an opening, which is larger than the hollow, and being on the first substrate wherein the opening encompasses the hollow, a first semiconductor chip being formed in the hollow, a second first semiconductor chip whose size is approximately the same as that of the first semiconductor chip, being supported by the first insulating substrate in an area, which encompasses the hollow.
    Type: Grant
    Filed: October 12, 2001
    Date of Patent: February 11, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Yuichi Morinaga, Kiyoshi Hasegawa, Kenji Fuchinoue
  • Publication number: 20020047214
    Abstract: A multi-chip package type semiconductor device includes a first insulating substrate having a hollow on its main surface, a second insulating substrate having on its main surface an opening, which is larger than the hollow, and being on the first substrate wherein the opening encompasses the hollow, a first semiconductor chip being formed in the hollow, a second first semiconductor chip whose size is approximately the same as that of the first semiconductor chip, being supported by the first insulating substrate in an area, which encompasses the hollow.
    Type: Application
    Filed: October 12, 2001
    Publication date: April 25, 2002
    Inventors: Yuichi Morinaga, Kiyoshi Hasegawa, Kenji Fuchinoue