Patents by Inventor Yuichi NAGAHISA
Yuichi NAGAHISA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240055306Abstract: The following steps (a) to (d) are provided. The step (a) is to form a drift layer of an n type on a silicon carbide semiconductor substrate of the n type through epitaxial growth. The step (b) is to measure impurity concentration of the drift layer. The step (c) is to form an ion implantation mask on the drift layer, the ion implantation mask including a plurality of first openings being periodically provided. The step (d) is to implant impurity ions of a p type through the plurality of first openings, form a plurality of second pillar regions of the p type in the drift layer, and turn the drift layer between the plurality of second pillar regions into a first pillar region. The step (d) includes performing feedforward control on an ion implantation amount so that there is a positive correlation with measurement results of the step (b).Type: ApplicationFiled: June 6, 2023Publication date: February 15, 2024Applicant: Mitsubishi Electric CorporationInventors: Yuichi NAGAHISA, Shigeto HONDA, Shinya AKAO, Shigehisa YAMAMOTO
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Publication number: 20230215921Abstract: A silicon carbide layer has an active region and an outer peripheral region arranged along an outer periphery of the active region in an in-plane direction. First well regions are arranged in the active region. A second well region is arranged in the outer peripheral region. Ohmic electrodes are arranged on a second surface of the silicon carbide layer, are connected to a source electrode, are electrically and ohmically connected to the first well regions, and have surface regions ohmically contacting a part forming the second surface of the silicon carbide layer and having a second conductivity type. The active region includes a standard region part and a thinned region part between the standard region part and the outer peripheral region. The surface regions are arranged at surface density lower in the thinned region part than in the standard region part in a plan view.Type: ApplicationFiled: August 11, 2020Publication date: July 6, 2023Applicant: Mitsubishi Electric CorporationInventors: Yuichi NAGAHISA, Takanori TANAKA, Hiroyuki AMISHIRO, Naoyuki KAWABATA
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Patent number: 11682723Abstract: In an SiC-MOSFET with a built-in Schottky diode, a bipolar current may be passed in a second well region formed at a terminal part to reduce the breakdown voltage of the terminal part. In the SiC-MOSFET with the built-in Schottky diode, a source electrode forming non-ohmic connection such as Schottky connection with the second well region is provided on the second well region formed below a gate pad in the terminal part. By the absence of ohmic connection between the second well region and the source electrode, reduction in breakdown voltage is suppressed at the terminal part.Type: GrantFiled: October 21, 2021Date of Patent: June 20, 2023Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Hideyuki Hatta, Shiro Hino, Koji Sadamatsu, Yuichi Nagahisa
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Patent number: 11646369Abstract: In an SiC-MOSFET with a built-in Schottky diode, a bipolar current may be passed in a second well region formed at a terminal part to reduce a breakdown voltage. In the SiC-MOSFET with the built-in Schottky diode, a conductive layer in Schottky connection with the second well region is provided on the second well region in the terminal part, and the conductive layer is electrically connected with a source electrode of the MOSFET. A conductive layer contact hole is provided for connecting only the conductive layer and the source electrode.Type: GrantFiled: March 16, 2021Date of Patent: May 9, 2023Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yuichi Nagahisa, Shiro Hino, Koji Sadamatsu, Hideyuki Hatta, Kotaro Kawahara
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Publication number: 20230133459Abstract: Fluctuations in device characteristics are suppressed by suppressing local occurrences of a large current through a body diode of a field-effect transistor. A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate, a semiconductor layer formed on the upper surface of the silicon carbide semiconductor substrate, and a backside electrode formed on the lower surface of the silicon carbide semiconductor substrate. A region in which electric resistivity takes a first value is regarded as a first resistance region, and a region where the electric resistivity takes a second value greater than the first value is regarded as a second resistance region. The second resistance region extends across a region boundary, i.e., the boundary between the active region and the termination region, in plan view.Type: ApplicationFiled: May 29, 2020Publication date: May 4, 2023Applicant: Mitsubishi Electric CorporationInventors: Takanori TANAKA, Yuichi NAGAHISA, Naoyuki KAWABATA, Hiroyuki AMISHIRO
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Publication number: 20230006045Abstract: The present disclosure has an object of providing a silicon carbide semiconductor device with high productivity which prevents characteristic degradation occurring when a large current is applied to a body diode. A structure including a SiC substrate, a buffer layer, and a drift layer is classified into an active region through which a current flows with application of a voltage to the SiC-MOSFET, and a breakdown voltage support region around a periphery of the active region in a plan view. The active region is classified into a first active region in a center portion, and a second active region between the first active region and the breakdown voltage support region in the plan view. Lifetimes of minority carriers in the second active region and the breakdown voltage support region are shorter than that in the first active region.Type: ApplicationFiled: January 27, 2020Publication date: January 5, 2023Applicant: Mitsubishi Electric CorporationInventors: Naoyuki KAWABATA, Yuichi NAGAHISA, Takanori TANAKA, Toshiaki IWAMATSU
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Patent number: 11508840Abstract: In SiC-MOSFETs including Schottky diodes, passage of a bipolar current to a second well region formed in a terminal portion sometimes reduces a breakdown voltage. In a SiC-MOSFET including Schottky diodes according to the present invention, the second well region formed in the terminal portion has a non-ohmic connection to a source electrode, and a field limiting layer lower in impurity concentration than the second well region is formed in a surface layer area of the second well region which is a region facing a gate electrode through a gate insulating film.Type: GrantFiled: May 28, 2020Date of Patent: November 22, 2022Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Shiro Hino, Yuichi Nagahisa, Koji Sadamatsu, Hideyuki Hatta, Kotaro Kawahara
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Publication number: 20220254906Abstract: An object of the present invention is to suppress the passage of bipolar current in a silicon carbide semiconductor device by reducing a voltage applied to a terminal well region during reflux operations. An SiC-MOSFET includes a plurality of first well regions, a second well region, a third well region in a surface layer of a drift layer, the first, second, and third well regions being of a second conductivity type. The third well region is provided on the side of the second well region opposite to the first well regions. A unit cell that includes the first well regions includes a unipolar diode. The SiC-MOSFET includes a source electrode connected to the unipolar diode and the ohmic electrode and not having ohmic connection with the second well region and the third well region.Type: ApplicationFiled: September 6, 2019Publication date: August 11, 2022Applicant: Mitsubishi Electric CorporationInventors: Yuichi NAGAHISA, Shiro HINO, Koji SADAMATSU, Kotaro KAWAHARA, Hideyuki HATTA, Shingo TOMOHISA
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Patent number: 11355627Abstract: In SiC-MOSFETs including Schottky diodes, passage of a bipolar current to a well region in a terminal region cannot be sufficiently reduced, which may reduce the reliability of elements. A SiC-MOSFET including Schottky diodes includes a gate electrode formed, through a second insulating film thicker than a gate insulating film in an active region, on a separation region between a first well region in the active region that is the closest to the terminal region and a second well region in the terminal region, wherein the second well region has a non-ohmic connection to a source electrode. Thus, a decrease in the reliability of elements is prevented.Type: GrantFiled: August 23, 2018Date of Patent: June 7, 2022Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yuichi Nagahisa, Shiro Hino, Hideyuki Hatta, Koji Sadamatsu
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Publication number: 20220045204Abstract: In an SiC-MOSFET with a built-in Schottky diode, a bipolar current may be passed in a second well region formed at a terminal part to reduce the breakdown voltage of the terminal part. In the SiC-MOSFET with the built-in Schottky diode, a source electrode forming non-ohmic connection such as Schottky connection with the second well region is provided on the second well region formed below a gate pad in the terminal part. By the absence of ohmic connection between the second well region and the source electrode, reduction in breakdown voltage is suppressed at the terminal part.Type: ApplicationFiled: October 21, 2021Publication date: February 10, 2022Applicant: Mitsubishi Electric CorporationInventors: Hideyuki HATTA, Shiro HINO, Koji SADAMATSU, Yuichi NAGAHISA
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Patent number: 11222973Abstract: A technique is provided for effectively suppressing a forward voltage shift due to occurrence of a stacking fault. A semiconductor device relating to the present technique includes a first well region of a second conductivity type, a second well region of the second conductivity type which is so provided as to sandwich the whole of a plurality of first well regions in a plan view and has an area larger than that of each of the first well regions, a third well region of the second conductivity type which is so provided as to sandwich the second well region in a plan view and has an area larger than that of the second well region, and a dividing region of a first conductivity type provided between the second well region and the third well region, having an upper surface which is in contact with an insulator.Type: GrantFiled: April 11, 2016Date of Patent: January 11, 2022Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Shiro Hino, Koji Sadamatsu, Hideyuki Hatta, Yuichi Nagahisa, Kohei Ebihara
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Patent number: 11189720Abstract: In an SiC-MOSFET with a built-in Schottky diode, a bipolar current may be passed in a second well region formed at a terminal part to reduce the breakdown voltage of the terminal part. In the SiC-MOSFET with the built-in Schottky diode, a source electrode forming non-ohmic connection such as Schottky connection with the second well region is provided on the second well region formed below a gate pad in the terminal part. By the absence of ohmic connection between the second well region and the source electrode, reduction in breakdown voltage is suppressed at the terminal part.Type: GrantFiled: February 22, 2018Date of Patent: November 30, 2021Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Hideyuki Hatta, Shiro Hino, Koji Sadamatsu, Yuichi Nagahisa
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Publication number: 20210226052Abstract: In an SiC-MOSFET with a built-in Schottky diode, a bipolar current may be passed in a second well region formed at a terminal part to reduce a breakdown voltage. In the SiC-MOSFET with the built-in Schottky diode, a conductive layer in Schottky connection with the second well region is provided on the second well region in the terminal part, and the conductive layer is electrically connected with a source electrode of the MOSFET. A conductive layer contact hole is provided for connecting only the conductive layer and the source electrode.Type: ApplicationFiled: March 16, 2021Publication date: July 22, 2021Applicant: Mitsubishi Electric CorporationInventors: Yuichi NAGAHISA, Shiro HINO, Koji SADAMATSU, Hideyuki HATTA, Kotaro KAWAHARA
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Patent number: 11049963Abstract: In SiC-MOSFETs including Schottky diodes, passage of a bipolar current to a well region in an edge portion of an active region cannot be sufficiently reduced, which may reduce the reliability of elements. In a SiC-MOSFET including Schottky diodes, the Schottky diodes formed in a terminal region are made higher in density in a plane direction than those formed in the active region or intervals between the Schottky diodes in the plane direction are shortened, without an ohmic connection between the well and the source in the terminal region.Type: GrantFiled: December 18, 2018Date of Patent: June 29, 2021Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Shiro Hino, Yuichi Nagahisa, Koji Sadamatsu, Hideyuki Hatta, Kotaro Kawahara
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Patent number: 10991822Abstract: In an SiC-MOSFET with a built-in Schottky diode, a bipolar current may be passed in a second well region formed at a terminal part to reduce a breakdown voltage. In the SiC-MOSFET with the built-in Schottky diode, a conductive layer in Schottky connection with the second well region is provided on the second well region in the terminal part, and the conductive layer is electrically connected with a source electrode of the MOSFET. A conductive layer contact hole is provided for connecting only the conductive layer and the source electrode.Type: GrantFiled: February 22, 2018Date of Patent: April 27, 2021Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yuichi Nagahisa, Shiro Hino, Koji Sadamatsu, Hideyuki Hatta, Kotaro Kawahara
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Publication number: 20200321462Abstract: In SiC-MOSFETs including Schottky diodes, passage of a bipolar current to a second well region formed in a terminal portion sometimes reduces a breakdown voltage. In a SiC-MOSFET including Schottky diodes according to the present invention, the second well region formed in the terminal portion has a non-ohmic connection to a source electrode, and a field limiting layer lower in impurity concentration than the second well region is formed in a surface layer area of the second well region which is a region facing a gate electrode through a gate insulating film.Type: ApplicationFiled: May 28, 2020Publication date: October 8, 2020Applicant: Mitsubishi Electric CorporationInventors: Shiro HINO, Yuichi NAGAHISA, Koji SADAMATSU, Hideyuki HATTA, Kotara KAWAHARA
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Publication number: 20200312995Abstract: In SiC-MOSFETs including Schottky diodes, passage of a bipolar current to a well region in a terminal region cannot be sufficiently reduced, which may reduce the reliability of elements. A SiC-MOSFET including Schottky diodes includes a gate electrode formed, through a second insulating film thicker than a gate insulating film in an active region, on a separation region between a first well region in the active region that is the closest to the terminal region and a second well region in the terminal region, wherein the second well region has a non-ohmic connection to a source electrode. Thus, a decrease in the reliability of elements is prevented.Type: ApplicationFiled: August 23, 2018Publication date: October 1, 2020Applicant: Mitsubishi Electric CorporationInventors: Yuichi NAGAHISA, Shiro HINO, Hideyuki HATTA, Koji SADAMATSU
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Publication number: 20200295177Abstract: In SiC-MOSFETs including Schottky diodes, passage of a bipolar current to a well region in an edge portion of an active region cannot be sufficiently reduced, which may reduce the reliability of elements. In a SiC-MOSFET including Schottky diodes, the Schottky diodes formed in a terminal region are made higher in density in a plane direction than those formed in the active region or intervals between the Schottky diodes in the plane direction are shortened, without an ohmic connection between the well and the source in the terminal region.Type: ApplicationFiled: December 18, 2018Publication date: September 17, 2020Applicant: Mitsubishi Electric CorporationInventors: Shiro HINO, Yuichi NAGAHISA, Koji SADAMATSU, Hideyuki HATTA, Kotaro KAWAHARA
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Publication number: 20190371935Abstract: In an SiC-MOSFET with a built-in Schottky diode, a bipolar current may be passed in a second well region formed at a terminal part to reduce the breakdown voltage of the terminal part. In the SiC-MOSFET with the built-in Schottky diode, a source electrode forming non-ohmic connection such as Schottky connection with the second well region is provided on the second well region formed below a gate pad in the terminal part. By the absence of ohmic connection between the second well region and the source electrode, reduction in breakdown voltage is suppressed at the terminal part.Type: ApplicationFiled: February 22, 2018Publication date: December 5, 2019Applicant: Mitsubishi Electric CorporationInventors: Hideyuki HATTA, Shiro HINO, Koji SADAMATSU, Yuichi NAGAHISA
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Publication number: 20190371936Abstract: In an SiC-MOSFET with a built-in Schottky diode, a bipolar current may be passed in a second well region formed at a terminal part to reduce a breakdown voltage. In the SiC-MOSFET with the built-in Schottky diode, a conductive layer in Schottky connection with the second well region is provided on the second well region in the terminal part, and the conductive layer is electrically connected with a source electrode of the MOSFET. A conductive layer contact hole is provided for connecting only the conductive layer and the source electrode.Type: ApplicationFiled: February 22, 2018Publication date: December 5, 2019Applicant: Mitsubishi Electric CorporationInventors: Yuichi NAGAHISA, Shiro HINO, Koji SADAMATSU, Hideyuki HATTA, Kotaro KAWAHARA