Patents by Inventor Yuichi Okuda
Yuichi Okuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11176888Abstract: A system includes a pixel that emits light based on a signal provided to the pixel. The system may also include a buffer circuit having a differential pair stage, a cascade stage, and an output stage. The differential pair stage may receive a common mode voltage signal via a first switch in response to the first switch receiving a first signal that causes the first switch to close. The differential pair stage may couple a capacitor to the output stage via a second switch that operate based on a second signal, such that the capacitor reduces an offset provided by one or more circuit components in the differential pair stage, the cascade stage, the output stage, or any combination thereof. The differential pair stage may output the common mode voltage to the pixel via the output stage in response to the first signal being present.Type: GrantFiled: June 18, 2020Date of Patent: November 16, 2021Assignee: Apple Inc.Inventors: Shingo Hatanaka, Derek Keith Shaeffer, John T. Wetherell, Nobutaka Shimamura, Yuichi Okuda, Jaeyoung Kang
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Publication number: 20210056930Abstract: An electronic device may include an electronic display having multiple display pixels. The display pixels may illuminate at a target luminance based at least in part on a first analog voltage signal. The electronic device may also include an electrical bus configured to generate multiple analog voltage signals including the first analog voltage signal, which is output on an output of the electrical bus. The electrical bus may include a digital to analog converter to generate at least some of the analog voltage signals and multiple output buffers to buffer the analog voltage signals. The outputs may be buffered by an output buffer of the output buffers.Type: ApplicationFiled: July 14, 2020Publication date: February 25, 2021Inventors: Jaeyoung Kang, Jesse Aaron Richmond, Mahdi Farrokh Baroughi, Hopil Bae, John T. Wetherell, Kingsuk Brahma, Yuichi Okuda, Shingo Hatanaka, Baris Cagdaser, Myungjoon Choi, Jie Won Ryu, Hyunwoo Nho, Yafei Bi, Wei H. Yao, Henry C. Jen, Derek Keith Shaeffer
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Publication number: 20210056904Abstract: A system includes a pixel that emits light based on a signal provided to the pixel. The system may also include a buffer circuit having a differential pair stage, a cascade stage, and an output stage. The differential pair stage may receive a common mode voltage signal via a first switch in response to the first switch receiving a first signal that causes the first switch to close. The differential pair stage may couple a capacitor to the output stage via a second switch that operate based on a second signal, such that the capacitor reduces an offset provided by one or more circuit components in the differential pair stage, the cascade stage, the output stage, or any combination thereof. The differential pair stage may output the common mode voltage to the pixel via the output stage in response to the first signal being present.Type: ApplicationFiled: June 18, 2020Publication date: February 25, 2021Inventors: Shingo Hatanaka, Derek Keith Shaeffer, John T. Wetherell, Nobutaka Shimamura, Yuichi Okuda, Jaeyoung Kang
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Patent number: 10310049Abstract: The present invention provides a semiconductor device and a failure detection method capable of detecting an excessive variation among elements that constitute an analog circuit as a failure. According to an embodiment, a semiconductor device 1 includes: an AD converter 11; a digital assist circuit 12 that corrects an error of a digital signal Do corresponding to an analog signal Ain processed by the AD converter 11; and a failure detection circuit 13 that detects whether the AD converter 11 has a failure based on a correction amount by the digital assist circuit. The semiconductor device 1 is therefore able to detect the excessive variation among the elements that constitute the AD converter 11 as a failure.Type: GrantFiled: July 23, 2016Date of Patent: June 4, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yuichi Okuda, Hideo Nakane, Takaya Yamamoto, Keisuke Kimura, Takashi Oshima
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Patent number: 10200059Abstract: A device includes a resistor string that includes a plurality resistors with voltage taps disposed therebetween. The device may select one particular voltage tap of the plurality of voltage taps based on received gray level data for a pixel of a display. The device also includes a first amplifier that may be coupled to a first terminal end of the resistor string. The device additionally includes a second amplifier that may be coupled to a second terminal end of the resistor string, wherein the plurality of voltage taps may each supply a tap voltage derived from a voltage between the first amplifier and the second amplifier, wherein any tap amplifier of the device coupled to a voltage tap of the plurality of voltage taps provides a reference voltage thereto.Type: GrantFiled: September 6, 2017Date of Patent: February 5, 2019Assignee: APPLE INC.Inventors: Baris Cagdaser, Derek K. Shaeffer, Hopil Bae, Jesse Aaron Richmond, Jie Won Ryu, Kingsuk Brahma, Mohammad B. Vahid Far, Shingo Hatanaka, Yafei Bi, Yuichi Okuda
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Patent number: 10020814Abstract: An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.Type: GrantFiled: May 15, 2017Date of Patent: July 10, 2018Assignee: Renesas Electronics CorporationInventors: Keisuke Kimura, Yuichi Okuda, Hideo Nakane, Takaya Yamamoto
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Patent number: 9960778Abstract: A semiconductor device according to an aspect of the invention relates to an AD converter that converts a signal level of an analog signal into a digital value by using a comparator, and determines an amount of adjustment of an offset voltage of the comparator based on an offset determination result of the comparator obtained immediately after a least significant bit (LSB) of a digital value output as a conversion result is converted.Type: GrantFiled: March 29, 2017Date of Patent: May 1, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Keisuke Kimura, Yuichi Okuda, Hideo Nakane, Takaya Yamamoto
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Publication number: 20180083648Abstract: A device includes a resistor string that includes a plurality resistors with voltage taps disposed therebetween. The device may select one particular voltage tap of the plurality of voltage taps based on received gray level data for a pixel of a display. The device also includes a first amplifier that may be coupled to a first terminal end of the resistor string. The device additionally includes a second amplifier that may be coupled to a second terminal end of the resistor string, wherein the plurality of voltage taps may each supply a tap voltage derived from a voltage between the first amplifier and the second amplifier, wherein any tap amplifier of the device coupled to a voltage tap of the plurality of voltage taps provides a reference voltage thereto.Type: ApplicationFiled: September 6, 2017Publication date: March 22, 2018Inventors: Baris Cagdaser, Derek K. Shaeffer, Hopil Bae, Jesse Aaron Richmond, Jie Won Ryu, Kingsuk Brahma, Mohammad B. Vahid Far, Shingo Hatanaka, Yafei Bi, Yuichi Okuda
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Patent number: 9891650Abstract: A current generation circuit including a first and a second bipolar transistors, a current distribution circuit that makes a first current and a second current flow through the first and second bipolar transistors, respectively, the first current and the second current corresponding to a first control voltage, a first NMOS transistor disposed between the first bipolar transistor and the first current distribution circuit, a second NMOS transistor disposed between the second bipolar transistor and the first current distribution circuit, a first resistive element, a first operational amplifier that outputs the second control voltage to the gates of the first and the second NMOS transistors according to a drain voltage of the first NMOS transistor and a reference bias voltage, and a second operational amplifier that generates the first control voltage according to a drain voltage of the second NMOS transistor and the reference bias voltage.Type: GrantFiled: May 17, 2017Date of Patent: February 13, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Atsushi Motozawa, Yuichi Okuda
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Publication number: 20170248984Abstract: A current generation circuit including a first and a second bipolar transistors, a current distribution circuit that makes a first current and a second current flow through the first and second bipolar transistors, respectively, the first current and the second current corresponding to a first control voltage, a first NMOS transistor disposed between the first bipolar transistor and the first current distribution circuit, a second NMOS transistor disposed between the second bipolar transistor and the first current distribution circuit, a first resistive element, a first operational amplifier that outputs the second control voltage to the gates of the first and the second NMOS transistors according to a drain voltage of the first NMOS transistor and a reference bias voltage, and a second operational amplifier that generates the first control voltage according to a drain voltage of the second NMOS transistor and the reference bias voltage.Type: ApplicationFiled: May 17, 2017Publication date: August 31, 2017Inventors: Atsushi MOTOZAWA, Yuichi OKUDA
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Publication number: 20170250697Abstract: An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.Type: ApplicationFiled: May 15, 2017Publication date: August 31, 2017Inventors: Keisuke KIMURA, Yuichi OKUDA, Hideo NAKANE, Takaya YAMAMOTO
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Publication number: 20170201264Abstract: A semiconductor device according to an aspect of the invention relates to an AD converter that converts a signal level of an analog signal into a digital value by using a comparator, and determines an amount of adjustment of an offset voltage of the comparator based on an offset determination result of the comparator obtained immediately after a least significant bit (LSB) of a digital value output as a conversion result is converted.Type: ApplicationFiled: March 29, 2017Publication date: July 13, 2017Inventors: Keisuke KIMURA, Yuichi OKUDA, Hideo NAKANE, Takaya YAMAMOTO
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Patent number: 9685968Abstract: An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.Type: GrantFiled: April 29, 2016Date of Patent: June 20, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Keisuke Kimura, Yuichi Okuda, Hideo Nakane, Takaya Yamamoto
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Patent number: 9678526Abstract: A current generation circuit including a first and a second bipolar transistors, a current distribution circuit that makes a first current and a second current flow through the first and second bipolar transistors, respectively, the first current and the second current corresponding to a first control voltage, a first NMOS transistor disposed between the first bipolar transistor and the first current distribution circuit, a second NMOS transistor disposed between the second bipolar transistor and the first current distribution circuit, a first resistive element, a first operational amplifier that outputs the second control voltage to the gates of the first and the second NMOS transistors according to a drain voltage of the first NMOS transistor and a reference bias voltage, and a second operational amplifier that generates the first control voltage according to a drain voltage of the second NMOS transistor and the reference bias voltage.Type: GrantFiled: March 26, 2015Date of Patent: June 13, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Atsushi Motozawa, Yuichi Okuda
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Patent number: 9641187Abstract: A semiconductor device according to an aspect of the invention relates to an AD converter that converts a signal level of an analog signal into a digital value by using a comparator, and determines an amount of adjustment of an offset voltage of the comparator based on an offset determination result of the comparator obtained immediately after a least significant bit (LSB) of a digital value output as a conversion result is converted.Type: GrantFiled: June 14, 2016Date of Patent: May 2, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Keisuke Kimura, Yuichi Okuda, Hideo Nakane, Takaya Yamamoto
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Patent number: 9628021Abstract: A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.Type: GrantFiled: February 15, 2016Date of Patent: April 18, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Osamu Ozawa, Masashi Horiguchi, Yuichi Okuda, Akihito Anzai
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Publication number: 20170045578Abstract: The present invention provides a semiconductor device and a failure detection method capable of detecting an excessive variation among elements that constitute an analog circuit as a failure. According to an embodiment, a semiconductor device 1 includes: an AD converter 11; a digital assist circuit 12 that corrects an error of a digital signal Do corresponding to an analog signal Ain processed by the AD converter 11; and a failure detection circuit 13 that detects whether the AD converter 11 has a failure based on a correction amount by the digital assist circuit. The semiconductor device 1 is therefore able to detect the excessive variation among the elements that constitute the AD converter 11 as a failure.Type: ApplicationFiled: July 23, 2016Publication date: February 16, 2017Inventors: Yuichi OKUDA, Hideo NAKANE, Takaya YAMAMOTO, Keisuke KIMURA, Takashi OSHIMA
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Publication number: 20160294403Abstract: A semiconductor device according to an aspect of the invention relates to an AD converter that converts a signal level of an analog signal into a digital value by using a comparator, and determines an amount of adjustment of an offset voltage of the comparator based on an offset determination result of the comparator obtained immediately after a least significant bit (LSB) of a digital value output as a conversion result is converted.Type: ApplicationFiled: June 14, 2016Publication date: October 6, 2016Inventors: Keisuke KIMURA, Yuichi OKUDA, Hideo NAKANE, Takaya YAMAMOTO
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Publication number: 20160248433Abstract: An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.Type: ApplicationFiled: April 29, 2016Publication date: August 25, 2016Inventors: Keisuke KIMURA, Yuichi OKUDA, Hideo NAKANE, Takaya YAMAMOTO
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Patent number: 9385736Abstract: A semiconductor device according to an aspect of the invention relates to an AD converter that converts a signal level of an analog signal into a digital value by using a comparator, and determines an amount of adjustment of an offset voltage of the comparator based on an offset determination result of the comparator obtained immediately after a least significant bit (LSB) of a digital value output as a conversion result is converted.Type: GrantFiled: October 23, 2015Date of Patent: July 5, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Keisuke Kimura, Yuichi Okuda, Hideo Nakane, Takaya Yamamoto