Patents by Inventor Yuichi Yato
Yuichi Yato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11444010Abstract: A semiconductor device includes: a semiconductor chip including a field effect transistor for switching; a die pad on which the semiconductor chip is mounted via a first bonding material; a lead electrically connected to a pad for source of the semiconductor chip through a metal plate; a lead coupling portion formed integrally with the lead; and a sealing portion for sealing them. A back surface electrode for drain of the semiconductor chip and the die pad are bonded via the first bonding material, the metal plate and the pad for source of the semiconductor chip are bonded via a second bonding material, and the metal plate and the lead coupling portion are bonded via a third bonding material. The first, second, and third bonding materials have conductivity, and an elastic modulus of each of the first and second bonding materials is lower than that of the third bonding material.Type: GrantFiled: October 1, 2020Date of Patent: September 13, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazunori Hasegawa, Yuichi Yato, Hiroyuki Nakamura, Yukihiro Sato, Hiroya Shimoyama
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Publication number: 20210118781Abstract: A semiconductor device includes: a semiconductor chip including a field effect transistor for switching; a die pad on which the semiconductor chip is mounted via a first bonding material; a lead electrically connected to a pad for source of the semiconductor chip through a metal plate; a lead coupling portion formed integrally with the lead; and a sealing portion for sealing them. A back surface electrode for drain of the semiconductor chip and the die pad are bonded via the first bonding material, the metal plate and the pad for source of the semiconductor chip are bonded via a second bonding material, and the metal plate and the lead coupling portion are bonded via a third bonding material. The first, second, and third bonding materials have conductivity, and an elastic modulus of each of the first and second bonding materials is lower than that of the third bonding material.Type: ApplicationFiled: October 1, 2020Publication date: April 22, 2021Inventors: Kazunori HASEGAWA, Yuichi YATO, Hiroyuki NAKAMURA, Yukihiro SATO, Hiroya SHIMOYAMA
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Patent number: 10818581Abstract: An improvement is achieved in the performance of a semiconductor device. A second component mounting portion over which a first electronic component is mounted is connected to a coupling portion of a lead frame via a suspension lead. The suspension lead has a first portion between the second component mounting portion and the coupling portion and a second portion between the first portion and the coupling portion. The second portion has a third portion connected to the first portion and having a width smaller than a width of the first portion, a fourth portion connected to the first portion and having a width smaller than the width of the first portion, and a through hole (opening) located between the third and fourth portions. Each of the first, third, and fourth portions has the same thickness. After a sealing body is formed, a cutting jig is pressed against the suspension lead to cut the suspension lead.Type: GrantFiled: July 22, 2017Date of Patent: October 27, 2020Assignee: Renesas Electronics CorporationInventors: Toshiyuki Hata, Yuichi Yato
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Patent number: 10347567Abstract: In a resin sealing type semiconductor device, a semiconductor chip CP2 is mounted over a die pad DP having conductivity via a bonding member BD2 having insulation property, and a semiconductor chip CP1 is mounted over the die pad DP via a bonding member BD1 having conductivity. A first length of a portion, in a first side formed by an intersection of a first side surface and a second side surface of the semiconductor chip CP2, covered with the bonding member BD2 is larger than a second length of a portion, in a second side formed by an intersection of a third side surface and a fourth side surface of the semiconductor chip CP1, covered with the bonding member BD1.Type: GrantFiled: June 27, 2018Date of Patent: July 9, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Atsushi Nishikizawa, Yuichi Yato, Hiroi Oka, Tadatoshi Danno, Hiroyuki Nakamura
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Publication number: 20180315685Abstract: In a resin sealing type semiconductor device, a semiconductor chip CP2 is mounted over a die pad DP having conductivity via a bonding member BD2 having insulation property, and a semiconductor chip CP1 is mounted over the die pad DP via a bonding member BD1 having conductivity. A first length of a portion, in a first side formed by an intersection of a first side surface and a second side surface of the semiconductor chip CP2, covered with the bonding member BD2 is larger than a second length of a portion, in a second side formed by an intersection of a third side surface and a fourth side surface of the semiconductor chip CP1, covered with the bonding member BD1.Type: ApplicationFiled: June 27, 2018Publication date: November 1, 2018Inventors: Atsushi NISHIKIZAWA, Yuichi YATO, Hiroi OKA, Tadatoshi DANNO, Hiroyuki NAKAMURA
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Patent number: 10037932Abstract: In a resin sealing type semiconductor device, a semiconductor chip CP2 is mounted over a die pad DP having conductivity via a bonding member BD2 having insulation property, and a semiconductor chip CP1 is mounted over the die pad DP via a bonding member BD1 having conductivity. A first length of a portion, in a first side formed by an intersection of a first side surface and a second side surface of the semiconductor chip CP2, covered with the bonding member BD2 is larger than a second length of a portion, in a second side formed by an intersection of a third side surface and a fourth side surface of the semiconductor chip CP1, covered with the bonding member BD1.Type: GrantFiled: March 30, 2015Date of Patent: July 31, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Atsushi Nishikizawa, Yuichi Yato, Hiroi Oka, Tadatoshi Danno, Hiroyuki Nakamura
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Publication number: 20180090420Abstract: An improvement is achieved in the performance of a semiconductor device. A second component mounting portion over which a first electronic component is mounted is connected to a coupling portion of a lead frame via a suspension lead. The suspension lead has a first portion between the second component mounting portion and the coupling portion and a second portion between the first portion and the coupling portion. The second portion has a third portion connected to the first portion and having a width smaller than a width of the first portion, a fourth portion connected to the first portion and having a width smaller than the width of the first portion, and a through hole (opening) located between the third and fourth portions. Each of the first, third, and fourth portions has the same thickness. After a sealing body is formed, a cutting jig is pressed against the suspension lead to cut the suspension lead.Type: ApplicationFiled: July 22, 2017Publication date: March 29, 2018Inventors: Toshiyuki HATA, Yuichi YATO
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Patent number: 9922905Abstract: A semiconductor device according to an embodiment is a semiconductor device in which a semiconductor chip mounted on a chip mounting part is sealed by resin and a first member is fixed to a chip mounting surface side between a peripheral portion of the semiconductor chip and a peripheral portion of the chip mounting part. Also, the first member is sealed by the resin. Also, a length of the first part of the chip mounting part in the first direction is larger than a length of the semiconductor chip in the first direction, in a plan view.Type: GrantFiled: February 28, 2017Date of Patent: March 20, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yuichi Yato, Hiroi Oka, Noriko Okunishi, Keita Takada
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Publication number: 20170221800Abstract: In a resin sealing type semiconductor device, a semiconductor chip CP2 is mounted over a die pad DP having conductivity via a bonding member BD2 having insulation property, and a semiconductor chip CP1 is mounted over the die pad DP via a bonding member BD1 having conductivity. A first length of a portion, in a first side formed by an intersection of a first side surface and a second side surface of the semiconductor chip CP2, covered with the bonding member BD2 is larger than a second length of a portion, in a second side formed by an intersection of a third side surface and a fourth side surface of the semiconductor chip CP1, covered with the bonding member BD1.Type: ApplicationFiled: March 30, 2015Publication date: August 3, 2017Inventors: Atsushi NISHIKIZAWA, Yuichi YATO, Hiroi OKA, Tadatoshi DANNO, Hiroyuki NAKAMURA
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Publication number: 20170170100Abstract: A semiconductor device according to an embodiment is a semiconductor device in which a semiconductor chip mounted on a chip mounting part is sealed by resin and a first member is fixed to a chip mounting surface side between a peripheral portion of the semiconductor chip and a peripheral portion of the chip mounting part. Also, the first member is sealed by the resin. Also, a length of the first part of the chip mounting part in the first direction is larger than a length of the semiconductor chip in the first direction, in a plan view.Type: ApplicationFiled: February 28, 2017Publication date: June 15, 2017Inventors: Yuichi YATO, Hiroi OKA, Noriko OKUNISHI, Keita TAKADA
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Patent number: 9607940Abstract: A semiconductor device according to an embodiment is a semiconductor device in which a semiconductor chip mounted on a chip mounting part is sealed by resin and a first member is fixed to a chip mounting surface side between a peripheral portion of the semiconductor chip and a peripheral portion of the chip mounting part. Also, the first member is sealed by the resin. Also, a length of the first part of the chip mounting part in the first direction is larger than a length of the semiconductor chip in the first direction, in a plan view.Type: GrantFiled: July 5, 2013Date of Patent: March 28, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yuichi Yato, Hiroi Oka, Noriko Okunishi, Keita Takada
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Publication number: 20160204057Abstract: A semiconductor device according to an embodiment is a semiconductor device in which a semiconductor chip mounted on a chip mounting part is sealed by resin and a first member is fixed to a chip mounting surface side between a peripheral portion of the semiconductor chip and a peripheral portion of the chip mounting part. Also, the first member is sealed by the resin. Also, a length of the first part of the chip mounting part in the first direction is larger than a length of the semiconductor chip in the first direction, in a plan view.Type: ApplicationFiled: July 5, 2013Publication date: July 14, 2016Inventors: Yuichi YATO, Hiroi OKA, Noriko OKUNISHI, Keita TAKADA
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Patent number: 9362238Abstract: A semiconductor device includes a first chip mounting portion, a first semiconductor chip arranged over the first chip mounting portion, a first pad formed in a surface of the first semiconductor chip, a first lead which serves as an external coupling terminal, a first conductive member which electrically couples the first pad and the first lead, and a sealing body which seals a part of the first chip mounting portion, the first semiconductor chip, a part of the first lead, and the first conductive member. The first conductive member includes a first plate-like portion, and a first support portion formed integrally with the first plate-like portion. An end of the first support portion is exposed from the sealing body, and the first support portion is formed with a first bent portion.Type: GrantFiled: October 21, 2015Date of Patent: June 7, 2016Assignee: Renesas Electronics CorporationInventors: Katsuhiko Funatsu, Yukihiro Sato, Yuichi Yato, Tomoaki Uno
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Publication number: 20160043042Abstract: A semiconductor device includes a first chip mounting portion, a first semiconductor chip arranged over the first chip mounting portion, a first pad formed in a surface of the first semiconductor chip, a first lead which serves as an external coupling terminal, a first conductive member which electrically couples the first pad and the first lead, and a sealing body which seals a part of the first chip mounting portion, the first semiconductor chip, a part of the first lead, and the first conductive member. The first conductive member includes a first plate-like portion, and a first support portion formed integrally with the first plate-like portion. An end of the first support portion is exposed from the sealing body, and the first support portion is formed with a first bent portion.Type: ApplicationFiled: October 21, 2015Publication date: February 11, 2016Inventors: Katsuhiko FUNATSU, Yukihiro SATO, Yuichi YATO, Tomoaki UNO
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Patent number: 9214412Abstract: A semiconductor device includes a first chip mounting portion, a first semiconductor chip arranged over the first chip mounting portion, a first pad formed in a surface of the first semiconductor chip, a first lead which serves as an external coupling terminal, a first conductive member which electrically couples the first pad and the first lead, and a sealing body which seals a part of the first chip mounting portion, the first semiconductor chip, a part of the first lead, and the first conductive member. The first conductive member includes a first plate-like portion, and a first support portion formed integrally with the first plate-like portion. An end of the first support portion is exposed from the sealing body, and the first support portion is formed with a first bent portion.Type: GrantFiled: June 15, 2014Date of Patent: December 15, 2015Assignee: Renesas Electronics CorporationInventors: Katsuhiko Funatsu, Yukihiro Sato, Yuichi Yato, Tomoaki Uno
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Publication number: 20150001699Abstract: A semiconductor device includes a first chip mounting portion, a first semiconductor chip arranged over the first chip mounting portion, a first pad formed in a surface of the first semiconductor chip, a first lead which serves as an external coupling terminal, a first conductive member which electrically couples the first pad and the first lead, and a sealing body which seals a part of the first chip mounting portion, the first semiconductor chip, a part of the first lead, and the first conductive member. The first conductive member includes a first plate-like portion, and a first support portion formed integrally with the first plate-like portion. An end of the first support portion is exposed from the sealing body, and the first support portion is formed with a first bent portion.Type: ApplicationFiled: June 15, 2014Publication date: January 1, 2015Inventors: Katsuhiko Funatsu, Yukihiro Sato, Yuichi Yato, Tomoaki Uno
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Publication number: 20140264383Abstract: A semiconductor device includes a die pad, an SiC chip mounted on the die pad, a porous first sintered Ag layer bonding the die pad and the SiC chip, and a reinforcing resin portion covering a surface of the first sintered Ag layer and formed in a fillet shape. The semiconductor device further includes a source lead electrically connected to a source electrode of the SiC chip, a gate lead electrically connected to a gate electrode, a drain lead electrically connected to a drain electrode, and a sealing body which covers the SiC chip, the first sintered Ag layer, and a part of the die pad, and the reinforcing resin portion covers a part of a side surface of the SiC chip.Type: ApplicationFiled: March 14, 2014Publication date: September 18, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Ryoichi KAJIWARA, Takuya NAKAJO, Katsuo ARAI, Yuichi YATO, Hiroi OKA, Hiroshi HOZOJI
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Patent number: 8643185Abstract: A die bonding portion is metallically bonded by well-conductive Cu metal powders with a maximum particle diameter of about 15 ?m to 200 ?m and adhesive layers of Ag, and minute holes are evenly dispersed in a joint layer. With this structure, the reflow resistance of about 260° C. and reliability under thermal cycle test can be ensured without using lead.Type: GrantFiled: October 7, 2008Date of Patent: February 4, 2014Assignee: Renesas Electronics CorporationInventors: Ryoichi Kajiwara, Kazutoshi Itou, Hiroi Oka, Takuya Nakajo, Yuichi Yato
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Publication number: 20130009300Abstract: A dug portion (50) in which a die-bonding material is filled is provided to a lower surface of a stamping nozzle (42) used in a step of applying the die-bonding material onto a chip mounting portion of a wiring board. Planar dimensions of the dug portion (50) are smaller than external dimensions of a chip to be mounted on the chip mounting portion. In addition, a depth of the dug portion (50) is smaller than a thickness of the chip. When the thickness of the chip is 100 ?m or smaller, a problem of crawling up of the die-bonding material to an upper surface of the chip is avoided by applying the die-bonding material onto the chip mounting portion using the stamping nozzle (42).Type: ApplicationFiled: March 31, 2010Publication date: January 10, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yuichi Yato, Hiroi Oka
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Patent number: 8252632Abstract: The present invention enables improvement of bonding reliability of the conductive adhesive interposed between a semiconductor chip and a die pad portion. Provided is a semiconductor device, in which a silicon chip is mounted over the die pad portion integrally formed with a drain lead, has a source pad over the main surface and a drain electrode of a power MOSFET over the back side, and is bonded onto the die pad portion via an Ag paste. In the device, a source lead and the source pad are electrically coupled via an Al ribbon. Over the back surface of the silicon chip, an Ag nanoparticle coated film is formed, while another Ag nanoparticle coated film is formed over the die pad portion and lead (drain lead and source lead).Type: GrantFiled: June 8, 2011Date of Patent: August 28, 2012Assignee: Renesas Electronics CorporationInventors: Yuichi Yato, Takuya Nakajo, Hiroi Oka