Patents by Inventor Yuichi Yato

Yuichi Yato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110237031
    Abstract: The present invention enables improvement of bonding reliability of the conductive adhesive interposed between a semiconductor chip and a die pad portion. Provided is a semiconductor device, in which a silicon chip is mounted over the die pad portion integrally formed with a drain lead, has a source pad over the main surface and a drain electrode of a power MOSFET over the back side, and is bonded onto the die pad portion via an Ag paste. In the device, a source lead and the source pad are electrically coupled via an Al ribbon. Over the back surface of the silicon chip, an Ag nanoparticle coated film is formed, while another Ag nanoparticle coated film is formed over the die pad portion and lead (drain lead and source lead).
    Type: Application
    Filed: June 8, 2011
    Publication date: September 29, 2011
    Inventors: Yuichi YATO, Takuya NAKAJO, Hiroi OKA
  • Patent number: 7977775
    Abstract: The present invention enables improvement of bonding reliability of the conductive adhesive interposed between a semiconductor chip and a die pad portion. Provided is a semiconductor device, in which a silicon chip is mounted over the die pad portion integrally formed with a drain lead, has a source pad over the main surface and a drain electrode of a power MOSFET over the back side, and is bonded onto the die pad portion via an Ag paste. In the device, a source lead and the source pad are electrically coupled via an Al ribbon. Over the back surface of the silicon chip, an Ag nanoparticle coated film is formed, while another Ag nanoparticle coated film is formed over the die pad portion and lead (drain lead and source lead).
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: July 12, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Yuichi Yato, Takuya Nakajo, Hiroi Oka
  • Publication number: 20090189264
    Abstract: The present invention enables improvement of bonding reliability of the conductive adhesive interposed between a semiconductor chip and a die pad portion. Provided is a semiconductor device, in which a silicon chip is mounted over the die pad portion integrally formed with a drain lead, has a source pad over the main surface and a drain electrode of a power MOSFET over the back side, and is bonded onto the die pad portion via an Ag paste. In the device, a source lead and the source pad are electrically coupled via an Al ribbon. Over the back surface of the silicon chip, an Ag nanoparticle coated film is formed, while another Ag nanoparticle coated film is formed over the die pad portion and lead (drain lead and source lead).
    Type: Application
    Filed: January 27, 2009
    Publication date: July 30, 2009
    Inventors: Yuichi Yato, Takuya Nakajo, Hiroi Oka
  • Publication number: 20090096100
    Abstract: A die bonding portion is metallically bonded by well-conductive Cu metal powders with a maximum particle diameter of about 15 ?m to 200 ?m and adhesive layers of Ag, and minute holes are evenly dispersed in a joint layer. With this structure, the reflow resistance of about 260° C. and reliability under thermal cycle test can be ensured without using lead.
    Type: Application
    Filed: October 7, 2008
    Publication date: April 16, 2009
    Inventors: Ryoichi KAJIWARA, Kazutoshi Itou, Hiroi Oka, Takuya Nakajo, Yuichi Yato