Patents by Inventor Yuichi Yokoyama

Yuichi Yokoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240164083
    Abstract: A microelectronic device comprises a stack structure comprising an array region comprising first conductive structures vertically spaced from one another, and a staircase region horizontally neighboring the array region and comprising second conductive structures vertically spaced from one another and coupled to the first conductive structures. The second conductive structures individually comprise portions extending in a first horizontal direction, and additional portions extending in a second horizontal direction transverse to the first horizontal direction. The staircase region comprises staircase structures having steps partially defined by edges of the second conductive structures. Some of the steps extend in the first horizontal direction and some others of the steps extend in the second horizontal direction. Related memory devices, electronic systems, and methods are also described.
    Type: Application
    Filed: November 10, 2022
    Publication date: May 16, 2024
    Inventor: Yuichi Yokoyama
  • Patent number: 11950403
    Abstract: Systems, methods, and apparatuses for widened conductive line structures and staircase structures for semiconductor devices are described herein. One memory device includes an array of vertically stacked memory cells, the array including a vertical stack of horizontally oriented conductive lines. Each conductive line comprises a first portion extending in a first horizontal direction and a second portion extending in a second horizontal direction, wherein the second portion of each conductive line is of a width greater than the first portion of each conductive line.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: April 2, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Yuichi Yokoyama
  • Patent number: 11949005
    Abstract: Provided is a semiconductor device that includes a first conductivity type well region below a gate runner portion, wherein a diode region includes first contact portions, a first conductivity type anode region, and a second conductivity type cathode region; wherein the well region contacts the diode region in the first direction, and when an end of the well region, an end of at least one of first contact portions, and an end of the cathode region that face one another in the first direction are imaginary projected on an upper surface of the semiconductor substrate, a first distance is longer than a second distance, the first distance being a distance between the end of the well region and the end of the cathode region, and the second distance being a distance between the end of the well region and the end of the at least one first contact portion.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: April 2, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Misaki Takahashi, Yuichi Harada, Kouta Yokoyama
  • Patent number: 11926230
    Abstract: Ease of connecting to a robot in a charging station is increased. A charging station includes a base having an upper face up on which a wheel rides, and a power supply terminal to be connected to a charging terminal of a robot. The upper face of the base is such that a target position is set in a far side region, while a reference entrance line that connects an entrance side specific position and the target position is set, and the upper face of the base includes an inverted face of a three-dimensional curved form that provides an entering wheel with a gravitational component that acts toward the reference entrance line side. The power supply terminal is connected to the charging terminal in a state wherein the wheel has arrived at the target position.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: March 12, 2024
    Assignee: GROOVE X, INC.
    Inventors: Kaname Hayashi, Daijiro Kato, Tomoaki Yokoyama, Yuichi Onda, Naoshi Hatori
  • Patent number: 11923573
    Abstract: A freight vehicle has a loading space, on which freight is loaded, rearward of a vehicle cabin in which an occupant rides. The freight vehicle includes a fuel cell mounted below the vehicle cabin and functioning as an electric power source, a storage portion disposed between the vehicle cabin and the loading space, and a tank disposed in the storage portion and stores fuel gas that is supplied to the fuel cell, and a radiator installed in the storage portion and performs heat exchange between air and a coolant that is supplied to the fuel cell.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: March 5, 2024
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, HINO MOTORS, LTD.
    Inventors: Yutaka Sawada, Yukihide Yokoyama, Yuichi Yagami
  • Publication number: 20240074144
    Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having a bottom electrode contact for an array of vertically stacked memory cells. The bottom electrode contact is formed in a periphery region. The bottom electrode contact is electrically coupled to a number of bottom electrodes of capacitors that are also formed in the periphery region.
    Type: Application
    Filed: November 7, 2023
    Publication date: February 29, 2024
    Inventors: Yuichi Yokoyama, Si-Woo Lee
  • Patent number: 11875947
    Abstract: Some embodiments include a capacitive unit having two or more capacitive tiers. Each of the capacitive tiers has first electrode material arranged in a configuration having laterally-extending first segments and longitudinally-extending second segments. The first and second segments join at intersection-regions. The first electrode material of the first and second segments is configured as tubes. The capacitive tiers are together configured as a stack having a first side. The first electrode material caps the tubes along the first side. Capacitor dielectric material lines the tubes. Second electrode material extends into the lined tubes. Columns of the second electrode material extend vertically through the capacitive tiers and are joined with the second electrode material within the lined tubes. A conductive plate extends vertically along the first side of the stack and is directly against the first electrode material. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: January 16, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Yuichi Yokoyama
  • Patent number: 11851130
    Abstract: A vehicle including a first member rotatably supporting a rear wheel, a second member disposed in front of the first member, and a coupling member disposed between the first member and the second member and fixed to the first member and the second member to support the first member and the second member swingably in a left-right direction about an axial line in a front-rear direction. The coupling member is provided so that a position of the post-swing ground contact point is closer to the axial line than a position of the post-swing ground contact point in the left-right direction before the first member swings, the ground contact point being a center in an area on a surface of the rear wheel in contact with a road surface, the post-swing ground contact point being the ground contact point after the first member swings about the axial line.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: December 26, 2023
    Assignee: Honda Motor Co., Ltd.
    Inventors: Mikio Kashiwai, Yotaro Mori, Tadahiro Yaguchi, Yuichi Yokoyama, Tomohiro Tsukamoto, Nobuo Kambara
  • Patent number: 11849573
    Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having a bottom electrode contact for an array of vertically stacked memory cells. The bottom electrode contact is formed in a periphery region. The bottom electrode contact is electrically coupled to a number of bottom electrodes of capacitors that are also formed in the periphery region.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: December 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Yuichi Yokoyama, Si-Woo Lee
  • Publication number: 20230052127
    Abstract: A vehicle including a first member rotatably supporting a rear wheel, a second member disposed in front of the first member, and a coupling member disposed between the first member and the second member and fixed to the first member and the second member to support the first member and the second member swingably in a left-right direction about an axial line in a front-rear direction. The coupling member is provided so that a position of the post-swing ground contact point is closer to the axial line than a position of the post-swing ground contact point in the left-right direction before the first member swings, the ground contact point being a center in an area on a surface of the rear wheel in contact with a road surface, the post-swing ground contact point being the ground contact point after the first member swings about the axial line.
    Type: Application
    Filed: January 14, 2021
    Publication date: February 16, 2023
    Inventors: Mikio Kashiwai, Yotaro Mori, Tadahiro Yaguchi, Yuichi Yokoyama, Tomohiro Tsukamoto, Nobuo Kambara
  • Patent number: 11476254
    Abstract: Systems, methods and apparatus are provided for support pillars in vertical three-dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and horizontally oriented storage nodes. The method includes depositing alternating layers of a dielectric material and a sacrificial material in repeating iterations to form a vertical stack. A plurality of spaced, first vertical openings are formed through the vertical stack adjacent areas where storage nodes will be formed. Support-pillar material is deposited in the plurality of spaced, first vertical openings to form structural support pillars. Second vertical openings are formed through the vertical stack adjacent the structural support pillars to define elongated vertical columns with first sidewalls of the alternating layers.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: October 18, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Yuichi Yokoyama
  • Publication number: 20220328249
    Abstract: Some embodiments include a capacitive unit having two or more capacitive tiers. Each of the capacitive tiers has first electrode material arranged in a configuration having laterally-extending first segments and longitudinally-extending second segments. The first and second segments join at intersection-regions. The first electrode material of the first and second segments is configured as tubes. The capacitive tiers are together configured as a stack having a first side. The first electrode material caps the tubes along the first side. Capacitor dielectric material lines the tubes. Second electrode material extends into the lined tubes. Columns of the second electrode material extend vertically through the capacitive tiers and are joined with the second electrode material within the lined tubes. A conductive plate extends vertically along the first side of the stack and is directly against the first electrode material. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: April 12, 2021
    Publication date: October 13, 2022
    Applicant: Micron Technology, Inc.
    Inventor: Yuichi Yokoyama
  • Publication number: 20220320000
    Abstract: Some embodiments include an integrated assembly having a first connection region with first contact pads. A second connection region is offset from the first connection region along a first direction. Second contact pads are within the second connection region. A memory array region is between the first and second connection regions. First conductive lines extend from the first contact pads of the first connection region and across the memory array region. Second conductive lines extend from the second contact pads of the second connection region and across the memory array region. The first conductive lines, second conductive lines, first contact pads and second contact pads have an identical conductive composition as one another. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: April 5, 2021
    Publication date: October 6, 2022
    Applicant: Micron Technology, Inc.
    Inventor: Yuichi Yokoyama
  • Publication number: 20220246618
    Abstract: Systems, methods and apparatus are provided for support pillars in vertical three-dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and horizontally oriented storage nodes. The method includes depositing alternating layers of a dielectric material and a sacrificial material in repeating iterations to form a vertical stack. A plurality of spaced, first vertical openings are formed through the vertical stack adjacent areas where storage nodes will be formed. Support-pillar material is deposited in the plurality of spaced, first vertical openings to form structural support pillars. Second vertical openings are formed through the vertical stack adjacent the structural support pillars to define elongated vertical columns with first sidewalls of the alternating layers.
    Type: Application
    Filed: January 29, 2021
    Publication date: August 4, 2022
    Inventor: Yuichi Yokoyama
  • Publication number: 20220208771
    Abstract: A method used in forming an array of capacitors comprises forming an array of vertically-elongated first capacitor electrodes that project vertically relative to an outer surface. An insulative ring is formed circumferentially about individual vertically-projecting portions of the first capacitor electrodes. The insulative rings about immediately-adjacent of the first capacitor electrodes in a first straight-line direction are laterally directly against one another. The insulative rings about immediately-adjacent of the first capacitor electrodes in a second straight-line direction that is angled relative to the first straight-line direction are laterally-spaced from one another. A capacitor insulator is formed over sidewalls of the first capacitor electrodes. At least one second capacitor electrode is formed over the capacitor insulator. Additional methods, including structure independent of method, are disclosed.
    Type: Application
    Filed: March 16, 2022
    Publication date: June 30, 2022
    Applicant: Micron Technology, Inc.
    Inventor: Yuichi Yokoyama
  • Publication number: 20220130830
    Abstract: Systems, methods, and apparatuses for widened conductive line structures and staircase structures for semiconductor devices are described herein. One memory device includes an array of vertically stacked memory cells, the array including a vertical stack of horizontally oriented conductive lines. Each conductive line comprises a first portion extending in a first horizontal direction and a second portion extending in a second horizontal direction, wherein the second portion of each conductive line is of a width greater than the first portion of each conductive line.
    Type: Application
    Filed: October 23, 2020
    Publication date: April 28, 2022
    Inventor: Yuichi Yokoyama
  • Patent number: 11309314
    Abstract: A method used in forming an array of capacitors comprises forming an array of vertically-elongated first capacitor electrodes that project vertically relative to an outer surface. An insulative ring is formed circumferentially about individual vertically-projecting portions of the first capacitor electrodes. The insulative rings about immediately-adjacent of the first capacitor electrodes in a first straight-line direction are laterally directly against one another. The insulative rings about immediately-adjacent of the first capacitor electrodes in a second straight-line direction that is angled relative to the first straight-line direction are laterally-spaced from one another. A capacitor insulator is formed over sidewalls of the first capacitor electrodes. At least one second capacitor electrode is formed over the capacitor insulator. Additional methods, including structure independent of method, are disclosed.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: April 19, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Yuichi Yokoyama
  • Patent number: 11299231
    Abstract: A steering structure for a saddle riding vehicle includes a suspension arm, a head pipe supported by a tip portion of a suspension arm, a stem shaft pivotably inserted through the head pipe, a front fork structure body integrally pivotably connected to a lower end portion of the stem shaft, a handle support section disposed above the head pipe, a handle steerably supported by the handle support section, and a bending link configured to transmit a steering operation of the handle toward a front wheel, wherein the bending link has an upper end portion connected to a side of the handle and a lower end portion connected to a side of the front fork structure body.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: April 12, 2022
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Masayuki Tsutsui, Kohei Suzuki, Takafumi Nakanishi, Yuichi Yokoyama
  • Publication number: 20220077150
    Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having a bottom electrode contact for an array of vertically stacked memory cells. The bottom electrode contact is formed in a periphery region. The bottom electrode contact is electrically coupled to a number of bottom electrodes of capacitors that are also formed in the periphery region.
    Type: Application
    Filed: September 10, 2020
    Publication date: March 10, 2022
    Inventors: Yuichi Yokoyama, Si-Woo Lee
  • Publication number: 20220028862
    Abstract: A method used in forming an array of capacitors comprises forming an array of vertically-elongated first capacitor electrodes that project vertically relative to an outer surface. An insulative ring is formed circumferentially about individual vertically-projecting portions of the first capacitor electrodes. The insulative rings about immediately-adjacent of the first capacitor electrodes in a first straight-line direction are laterally directly against one another. The insulative rings about immediately-adjacent of the first capacitor electrodes in a second straight-line direction that is angled relative to the first straight-line direction are laterally-spaced from one another. A capacitor insulator is formed over sidewalls of the first capacitor electrodes. At least one second capacitor electrode is formed over the capacitor insulator. Additional methods, including structure independent of method, are disclosed.
    Type: Application
    Filed: July 22, 2020
    Publication date: January 27, 2022
    Applicant: Micron Technology, Inc.
    Inventor: Yuichi Yokoyama