Patents by Inventor Yuichi Yokoyama
Yuichi Yokoyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250112151Abstract: A microelectronic device includes a stack structure with tiers individually extending through an array area and into a staircase area horizontally neighboring the array area. The array area includes at least one access device. The staircase area includes a staircase structure having steps at ends of the tiers. At least some of the tiers individually include a conductive region, insulative regions, and discrete regions of semiconductor material. The conductive region includes conductive material extending through the array area and into the staircase area. The insulative regions are in both the array area and the staircase area. The discrete regions of semiconductor material are in the array area. The staircase area is substantially free of the semiconductor material. The conductive material is thicker in the staircase area than in the array area. Related electronic systems and methods of formation are also disclosed.Type: ApplicationFiled: July 23, 2024Publication date: April 3, 2025Inventors: Si-Woo Lee, Scott E. Sills, Yuichi Yokoyama
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Publication number: 20250056828Abstract: Some implementations herein provide for a memory device and methods of formation. The memory device includes a plurality of storage cells arranged vertically and a plurality of corresponding gate all around transistors. Methods of forming the memory device include using a single trench to remove a liner material and form recesses that define cell contact lightly-doped drain regions of the gate all around transistors. Using the single trench to remove the liner material and form the recesses that define the cell contact lightly-doped drain region widths causes the cell contact lightly-doped drain regions to be formed having substantially similar widths.Type: ApplicationFiled: July 24, 2024Publication date: February 13, 2025Inventors: Si-Woo LEE, Yuichi YOKOYAMA, Scott E. SILLS, Gautham MUTHUSAMY, David HWANG, Yoshitaka NAKAMURA, Pavani Vamsi Krishna NITTALA, Yuanzhi MA, Glen H. WALTERS, Haitao LIU, Kamal M. KARDA
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Publication number: 20250040121Abstract: Methods, systems, and devices for multi-layer capacitors for three-dimensional memory systems are described. Memory cells of a memory system may include capacitors having dielectric material between multiple interfaces (e.g., concentric interfaces) of a bottom electrode and a top electrode. A bottom electrode may include a first portion wrapping around a portion of a semiconductor material that is contiguous with a channel of a transistor, and a top electrode may include a first portion wrapping around the first portion of the bottom electrode. The bottom electrode may also include a second portion wrapping around the first portion of the top electrode, and the top electrode may also include a second portion wrapping around the second portion of the bottom electrode. The dielectric material may include respective portions between each interface of the bottom electrode and top electrode which, in some examples, may be a contiguous implementation of the dielectric material.Type: ApplicationFiled: July 18, 2024Publication date: January 30, 2025Inventors: Yuanzhi Ma, Scott E. Sills, Si-Woo Lee, David K. Hwang, Yoshitaka Nakamura, Yuichi Yokoyama, Pavani Vamsi Krishna Nittala, Glen H. Walters, Gautham Muthusamy, Haitao Liu, Kamal Karda
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Publication number: 20240164083Abstract: A microelectronic device comprises a stack structure comprising an array region comprising first conductive structures vertically spaced from one another, and a staircase region horizontally neighboring the array region and comprising second conductive structures vertically spaced from one another and coupled to the first conductive structures. The second conductive structures individually comprise portions extending in a first horizontal direction, and additional portions extending in a second horizontal direction transverse to the first horizontal direction. The staircase region comprises staircase structures having steps partially defined by edges of the second conductive structures. Some of the steps extend in the first horizontal direction and some others of the steps extend in the second horizontal direction. Related memory devices, electronic systems, and methods are also described.Type: ApplicationFiled: November 10, 2022Publication date: May 16, 2024Inventor: Yuichi Yokoyama
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Patent number: 11950403Abstract: Systems, methods, and apparatuses for widened conductive line structures and staircase structures for semiconductor devices are described herein. One memory device includes an array of vertically stacked memory cells, the array including a vertical stack of horizontally oriented conductive lines. Each conductive line comprises a first portion extending in a first horizontal direction and a second portion extending in a second horizontal direction, wherein the second portion of each conductive line is of a width greater than the first portion of each conductive line.Type: GrantFiled: October 23, 2020Date of Patent: April 2, 2024Assignee: Micron Technology, Inc.Inventor: Yuichi Yokoyama
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Publication number: 20240074144Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having a bottom electrode contact for an array of vertically stacked memory cells. The bottom electrode contact is formed in a periphery region. The bottom electrode contact is electrically coupled to a number of bottom electrodes of capacitors that are also formed in the periphery region.Type: ApplicationFiled: November 7, 2023Publication date: February 29, 2024Inventors: Yuichi Yokoyama, Si-Woo Lee
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Patent number: 11875947Abstract: Some embodiments include a capacitive unit having two or more capacitive tiers. Each of the capacitive tiers has first electrode material arranged in a configuration having laterally-extending first segments and longitudinally-extending second segments. The first and second segments join at intersection-regions. The first electrode material of the first and second segments is configured as tubes. The capacitive tiers are together configured as a stack having a first side. The first electrode material caps the tubes along the first side. Capacitor dielectric material lines the tubes. Second electrode material extends into the lined tubes. Columns of the second electrode material extend vertically through the capacitive tiers and are joined with the second electrode material within the lined tubes. A conductive plate extends vertically along the first side of the stack and is directly against the first electrode material. Some embodiments include methods of forming integrated assemblies.Type: GrantFiled: April 12, 2021Date of Patent: January 16, 2024Assignee: Micron Technology, Inc.Inventor: Yuichi Yokoyama
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Patent number: 11851130Abstract: A vehicle including a first member rotatably supporting a rear wheel, a second member disposed in front of the first member, and a coupling member disposed between the first member and the second member and fixed to the first member and the second member to support the first member and the second member swingably in a left-right direction about an axial line in a front-rear direction. The coupling member is provided so that a position of the post-swing ground contact point is closer to the axial line than a position of the post-swing ground contact point in the left-right direction before the first member swings, the ground contact point being a center in an area on a surface of the rear wheel in contact with a road surface, the post-swing ground contact point being the ground contact point after the first member swings about the axial line.Type: GrantFiled: January 14, 2021Date of Patent: December 26, 2023Assignee: Honda Motor Co., Ltd.Inventors: Mikio Kashiwai, Yotaro Mori, Tadahiro Yaguchi, Yuichi Yokoyama, Tomohiro Tsukamoto, Nobuo Kambara
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Patent number: 11849573Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having a bottom electrode contact for an array of vertically stacked memory cells. The bottom electrode contact is formed in a periphery region. The bottom electrode contact is electrically coupled to a number of bottom electrodes of capacitors that are also formed in the periphery region.Type: GrantFiled: September 10, 2020Date of Patent: December 19, 2023Assignee: Micron Technology, Inc.Inventors: Yuichi Yokoyama, Si-Woo Lee
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Publication number: 20230052127Abstract: A vehicle including a first member rotatably supporting a rear wheel, a second member disposed in front of the first member, and a coupling member disposed between the first member and the second member and fixed to the first member and the second member to support the first member and the second member swingably in a left-right direction about an axial line in a front-rear direction. The coupling member is provided so that a position of the post-swing ground contact point is closer to the axial line than a position of the post-swing ground contact point in the left-right direction before the first member swings, the ground contact point being a center in an area on a surface of the rear wheel in contact with a road surface, the post-swing ground contact point being the ground contact point after the first member swings about the axial line.Type: ApplicationFiled: January 14, 2021Publication date: February 16, 2023Inventors: Mikio Kashiwai, Yotaro Mori, Tadahiro Yaguchi, Yuichi Yokoyama, Tomohiro Tsukamoto, Nobuo Kambara
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Patent number: 11476254Abstract: Systems, methods and apparatus are provided for support pillars in vertical three-dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and horizontally oriented storage nodes. The method includes depositing alternating layers of a dielectric material and a sacrificial material in repeating iterations to form a vertical stack. A plurality of spaced, first vertical openings are formed through the vertical stack adjacent areas where storage nodes will be formed. Support-pillar material is deposited in the plurality of spaced, first vertical openings to form structural support pillars. Second vertical openings are formed through the vertical stack adjacent the structural support pillars to define elongated vertical columns with first sidewalls of the alternating layers.Type: GrantFiled: January 29, 2021Date of Patent: October 18, 2022Assignee: Micron Technology, Inc.Inventor: Yuichi Yokoyama
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Publication number: 20220328249Abstract: Some embodiments include a capacitive unit having two or more capacitive tiers. Each of the capacitive tiers has first electrode material arranged in a configuration having laterally-extending first segments and longitudinally-extending second segments. The first and second segments join at intersection-regions. The first electrode material of the first and second segments is configured as tubes. The capacitive tiers are together configured as a stack having a first side. The first electrode material caps the tubes along the first side. Capacitor dielectric material lines the tubes. Second electrode material extends into the lined tubes. Columns of the second electrode material extend vertically through the capacitive tiers and are joined with the second electrode material within the lined tubes. A conductive plate extends vertically along the first side of the stack and is directly against the first electrode material. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: April 12, 2021Publication date: October 13, 2022Applicant: Micron Technology, Inc.Inventor: Yuichi Yokoyama
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Publication number: 20220320000Abstract: Some embodiments include an integrated assembly having a first connection region with first contact pads. A second connection region is offset from the first connection region along a first direction. Second contact pads are within the second connection region. A memory array region is between the first and second connection regions. First conductive lines extend from the first contact pads of the first connection region and across the memory array region. Second conductive lines extend from the second contact pads of the second connection region and across the memory array region. The first conductive lines, second conductive lines, first contact pads and second contact pads have an identical conductive composition as one another. Some embodiments include methods of forming integrated assemblies.Type: ApplicationFiled: April 5, 2021Publication date: October 6, 2022Applicant: Micron Technology, Inc.Inventor: Yuichi Yokoyama
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Publication number: 20220246618Abstract: Systems, methods and apparatus are provided for support pillars in vertical three-dimensional (3D) memory. An example method includes a method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and horizontally oriented storage nodes. The method includes depositing alternating layers of a dielectric material and a sacrificial material in repeating iterations to form a vertical stack. A plurality of spaced, first vertical openings are formed through the vertical stack adjacent areas where storage nodes will be formed. Support-pillar material is deposited in the plurality of spaced, first vertical openings to form structural support pillars. Second vertical openings are formed through the vertical stack adjacent the structural support pillars to define elongated vertical columns with first sidewalls of the alternating layers.Type: ApplicationFiled: January 29, 2021Publication date: August 4, 2022Inventor: Yuichi Yokoyama
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Publication number: 20220208771Abstract: A method used in forming an array of capacitors comprises forming an array of vertically-elongated first capacitor electrodes that project vertically relative to an outer surface. An insulative ring is formed circumferentially about individual vertically-projecting portions of the first capacitor electrodes. The insulative rings about immediately-adjacent of the first capacitor electrodes in a first straight-line direction are laterally directly against one another. The insulative rings about immediately-adjacent of the first capacitor electrodes in a second straight-line direction that is angled relative to the first straight-line direction are laterally-spaced from one another. A capacitor insulator is formed over sidewalls of the first capacitor electrodes. At least one second capacitor electrode is formed over the capacitor insulator. Additional methods, including structure independent of method, are disclosed.Type: ApplicationFiled: March 16, 2022Publication date: June 30, 2022Applicant: Micron Technology, Inc.Inventor: Yuichi Yokoyama
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Publication number: 20220130830Abstract: Systems, methods, and apparatuses for widened conductive line structures and staircase structures for semiconductor devices are described herein. One memory device includes an array of vertically stacked memory cells, the array including a vertical stack of horizontally oriented conductive lines. Each conductive line comprises a first portion extending in a first horizontal direction and a second portion extending in a second horizontal direction, wherein the second portion of each conductive line is of a width greater than the first portion of each conductive line.Type: ApplicationFiled: October 23, 2020Publication date: April 28, 2022Inventor: Yuichi Yokoyama
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Patent number: 11309314Abstract: A method used in forming an array of capacitors comprises forming an array of vertically-elongated first capacitor electrodes that project vertically relative to an outer surface. An insulative ring is formed circumferentially about individual vertically-projecting portions of the first capacitor electrodes. The insulative rings about immediately-adjacent of the first capacitor electrodes in a first straight-line direction are laterally directly against one another. The insulative rings about immediately-adjacent of the first capacitor electrodes in a second straight-line direction that is angled relative to the first straight-line direction are laterally-spaced from one another. A capacitor insulator is formed over sidewalls of the first capacitor electrodes. At least one second capacitor electrode is formed over the capacitor insulator. Additional methods, including structure independent of method, are disclosed.Type: GrantFiled: July 22, 2020Date of Patent: April 19, 2022Assignee: Micron Technology, Inc.Inventor: Yuichi Yokoyama
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Patent number: 11299231Abstract: A steering structure for a saddle riding vehicle includes a suspension arm, a head pipe supported by a tip portion of a suspension arm, a stem shaft pivotably inserted through the head pipe, a front fork structure body integrally pivotably connected to a lower end portion of the stem shaft, a handle support section disposed above the head pipe, a handle steerably supported by the handle support section, and a bending link configured to transmit a steering operation of the handle toward a front wheel, wherein the bending link has an upper end portion connected to a side of the handle and a lower end portion connected to a side of the front fork structure body.Type: GrantFiled: September 23, 2019Date of Patent: April 12, 2022Assignee: HONDA MOTOR CO., LTD.Inventors: Masayuki Tsutsui, Kohei Suzuki, Takafumi Nakanishi, Yuichi Yokoyama
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Publication number: 20220077150Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having a bottom electrode contact for an array of vertically stacked memory cells. The bottom electrode contact is formed in a periphery region. The bottom electrode contact is electrically coupled to a number of bottom electrodes of capacitors that are also formed in the periphery region.Type: ApplicationFiled: September 10, 2020Publication date: March 10, 2022Inventors: Yuichi Yokoyama, Si-Woo Lee
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Publication number: 20220028862Abstract: A method used in forming an array of capacitors comprises forming an array of vertically-elongated first capacitor electrodes that project vertically relative to an outer surface. An insulative ring is formed circumferentially about individual vertically-projecting portions of the first capacitor electrodes. The insulative rings about immediately-adjacent of the first capacitor electrodes in a first straight-line direction are laterally directly against one another. The insulative rings about immediately-adjacent of the first capacitor electrodes in a second straight-line direction that is angled relative to the first straight-line direction are laterally-spaced from one another. A capacitor insulator is formed over sidewalls of the first capacitor electrodes. At least one second capacitor electrode is formed over the capacitor insulator. Additional methods, including structure independent of method, are disclosed.Type: ApplicationFiled: July 22, 2020Publication date: January 27, 2022Applicant: Micron Technology, Inc.Inventor: Yuichi Yokoyama