Patents by Inventor Yuichiro Mitani

Yuichiro Mitani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6891238
    Abstract: A semiconductor device including a silicon substrate, a gate insulator film formed on the silicon substrate and including silicon, deuterium, and at least one of oxygen and nitrogen, and a gate electrode formed on the gate insulator film wherein a deuterium concentration in a vicinity of an interface of the gate insulator film with the gate electrode is at least 1×107 cm?3, and a deuterium concentration in a vicinity of an interface of the gate insulator film with the silicon substrate is higher than the deuterium concentration in the vicinity of the interface of the gate insulation film with the gate electrode.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: May 10, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichiro Mitani, Hideki Satake
  • Publication number: 20050009306
    Abstract: A method of manufacturing a semiconductor device comprises a step of depositing a crystalline insulating layer oriented in a predetermined crystal face orientation by epitaxial growth on an amorphous semiconductor layer, a step of depositing a second amorphous semiconductor layer on the crystalline insulating layer, a step of growing said first and second semiconductor layers into a polycrystal or single crystal layer in a solid phase, using said crystalline insulating film as core, and a step of forming a functional element containing said first and second semiconductor layer.
    Type: Application
    Filed: August 4, 2004
    Publication date: January 13, 2005
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuichiro Mitani, Yukie Nishikawa
  • Publication number: 20040251521
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.
    Type: Application
    Filed: July 1, 2004
    Publication date: December 16, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masayuki Tanaka, Yoshio Ozawa, Shigehiko Saida, Akira Goda, Mitsuhiro Noguchi, Yuichiro Mitani, Yoshitaka Tsunashima
  • Publication number: 20040227198
    Abstract: A semiconductor device including a silicon substrate, a gate insulator film formed on the silicon substrate and including silicon, deuterium, and at least one of oxygen and nitrogen, and a gate electrode formed on the gate insulator film wherein a deuterium concentration in a vicinity of an interface of the gate insulator film with the gate electrode is at least 1×1017 cm−3, and a deuterium concentration in a vicinity of an interface of the gate insulator film with the silicon substrate is higher than the deuterium concentration in the vicinity of the interface of the gate insulation film with the gate electrode.
    Type: Application
    Filed: June 22, 2004
    Publication date: November 18, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuichiro Mitani, Hideki Satake
  • Patent number: 6787433
    Abstract: A method of manufacturing a semiconductor device comprises a step of depositing a crystalline insulating layer oriented in a predetermined crystal face orientation by epitaxial growth on an amorphous semiconductor layer, a step of depositing a second amorphous semiconductor layer on the crystalline insulating layer, a step of growing said first and second semiconductor layers into a polycrystal or single crystal layer in a solid phase, using said crystalline insulating film as core, and a step of forming a functional element containing said first and second semiconductor layer.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: September 7, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichiro Mitani, Yukie Nishikawa
  • Patent number: 6774462
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.
    Type: Grant
    Filed: October 24, 2002
    Date of Patent: August 10, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Tanaka, Yoshio Ozawa, Shigehiko Saida, Akira Goda, Mitsuhiro Noguchi, Yuichiro Mitani, Yoshitaka Tsunashima
  • Publication number: 20030222318
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.
    Type: Application
    Filed: October 24, 2002
    Publication date: December 4, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masayuki Tanaka, Yoshio Ozawa, Shigehiko Saida, Akira Goda, Mitsuhiro Noguchi, Yuichiro Mitani, Yoshitaka Tsunashima
  • Publication number: 20030057491
    Abstract: A method of manufacturing a semiconductor device comprises a step of depositing a crystalline insulating layer oriented in a predetermined crystal face orientation by epitaxial growth on an amorphous semiconductor layer, a step of depositing a second amorphous semiconductor layer on the crystalline insulating layer, a step of growing said first and second semiconductor layers into a polycrystal or single crystal layer in a solid phase, using said crystalline insulating film as core, and a step of forming a functional element containing said first and second semiconductor layer.
    Type: Application
    Filed: September 19, 2002
    Publication date: March 27, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuichiro Mitani, Yukie Nishikawa
  • Publication number: 20020140043
    Abstract: A semiconductor device including a silicon substrate, a gate insulator film formed on the silicon substrate and including silicon, deuterium, and at least one of oxygen and nitrogen, and a gate electrode formed on the gate insulator film wherein a deuterium concentration in a vicinity of an interface of the gate insulator film with the gate electrode is at least 1×107 cm−3, and a deuterium concentration in a vicinity of an interface of the gate insulator film with the silicon substrate is higher than the deuterium concentration in the vicinity of the interface of the gate insulation film with the gate electrode.
    Type: Application
    Filed: April 1, 2002
    Publication date: October 3, 2002
    Applicant: KABUSHI KAISHA TOSHIBA
    Inventors: Yuichiro Mitani, Hideki Satake
  • Patent number: 6395621
    Abstract: A process is provided with which amorphous silicon or polysilicon is deposited on a semiconductor substrate. Then, a low-temperature solid phase growth method is employed to selectively form amorphous silicon or polysilicon into single crystal silicon on only an exposed portion of the semiconductor substrate. A step for manufacturing an epitaxial silicon substrate a exhibiting a high manufacturing yield, a low cost and high quality can be employed in a process for manufacturing a semiconductor device incorporating a shrinked MOS transistor. Specifically, a silicon oxide layer having a thickness which is not larger than the mono-molecular layer is formed on the silicon substrate. Then, an amorphous silicon layer is deposited on the silicon oxide layer in a low-temperature region to perform annealing in the low-temperature region. Thus, the amorphous silicon layer is changed into a single crystal owing to solid phase growth.
    Type: Grant
    Filed: December 3, 2001
    Date of Patent: May 28, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Mizushima, Yuichiro Mitani, Shigeru Kambayashi, Kiyotaka Miyano
  • Publication number: 20020034864
    Abstract: A process is provided with which amorphous silicon or polysilicon is deposited on a semiconductor substrate. Then, a low-temperature solid phase growth method is employed to selectively form amorphous silicon or polysilicon into single crystal silicon on only an exposed portion of the semiconductor substrate. A step for manufacturing an epitaxial silicon substrate exhibiting a high manufacturing yield, a low cost and high quality can be employed in a process for manufacturing a semiconductor device incorporating a shrinked MOS transistor. Specifically, a silicon oxide layer having a thickness which is not larger than the mono-molecular layer is formed on the silicon substrate. Then, an amorphous silicon layer is deposited on the silicon oxide layer in a low-temperature region to perform annealing in the low-temperature region. Thus, the amorphous silicon layer is changed into a single crystal owing to solid phase growth.
    Type: Application
    Filed: December 3, 2001
    Publication date: March 21, 2002
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Mizushima, Yuichiro Mitani, Shigeru Kambayashi, Kiyotaka Miyano
  • Patent number: 6346732
    Abstract: A process is provided with which amorphous silicon or polysilicon is deposited on a semiconductor substrate. Then, a low-temperature solid phase growth method is employed to selectively form amorphous silicon or polysilicon into single crystal silicon on only an exposed portion of the semiconductor substrate. A step for manufacturing an epitaxial silicon substrate exhibiting a high manufacturing yield, a low cost and high quality can be employed in a process for manufacturing a semiconductor device incorporating a shrinked MOS transistor. Specifically, a silicon oxide layer having a thickness which is not larger than the mono-molecular layer is formed on the silicon substrate. Then, an amorphous silicon layer is deposited on the silicon oxide layer in a low-temperature region to perform annealing in the low-temperature region. Thus, the amorphous silicon layer is changed into a single crystal owing to solid phase growth.
    Type: Grant
    Filed: May 11, 2000
    Date of Patent: February 12, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Mizushima, Yuichiro Mitani, Shigeru Kambayashi, Kiyotaka Miyano
  • Patent number: 6342421
    Abstract: A method of manufacturing a semiconductor device including the steps of forming an insulating film on a silicon region of a substrate having the silicon region on a surface the insulating film having an opening for forming an exposed region of the silicon region, supplying a gas containing a halogen onto the silicon region, and supplying a source gas of silicon onto the silicon region, thereby selectively depositing the silicon on the exposed region of the silicon region.
    Type: Grant
    Filed: June 18, 1998
    Date of Patent: January 29, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichiro Mitani, Ichiro Mizushima, Shigeru Kambayashi, Hirotaka Nishino, Masahiro Kashiwagi
  • Patent number: 6191463
    Abstract: A semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, and an electrode formed on the first insulating film. The first insulating film contains a halogen element and a combination of silicon and nitrogen or a combination of silicon, oxygen, and nitrogen. The maximum concentration of the halogen element in the first insulating film ranges from 1020 atoms/cm3 to 1021 atoms/cm3 inclusive. With this structure, the dielectric breakdown strength and the like of the insulating film increase, and the reliability of the insulating film improves.
    Type: Grant
    Filed: July 14, 1998
    Date of Patent: February 20, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichiro Mitani, Hideki Satake, Akira Toriumi
  • Patent number: 6018185
    Abstract: The semiconductor device comprises a semiconductor substrate having an element region, an element isolation film formed on the semiconductor substrate so as to surround the element region, a gate portion crossing the element region and extending over the semiconductor substrate, the gate portion comprising at least a gate insulation film formed on the semiconcuctor substrate and a gate electrode formed on the gate insulation film, and source/drain regions formed on the surface of the element regions on both sides of the gate portion, wherein an upper surface of the element isolation film is formed in substantially the same plane as an upper surface of the gate portion.
    Type: Grant
    Filed: May 21, 1997
    Date of Patent: January 25, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichiro Mitani, Ichiro Mizushima, Shigeru Kambayashi, Iwao Kunishima, Masahiro Kashiwagi
  • Patent number: 5864161
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming an insulating film on a silicon region of a substrate having the silicon region on a surface the insulating film having an opening for forming an exposed region of the silicon region, supplying a gas containing a halogen onto the silicon region, and supplying a source gas of silicon onto the silicon region, thereby selectively depositing the silicon on the exposed region of the silicon region.
    Type: Grant
    Filed: September 11, 1995
    Date of Patent: January 26, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichiro Mitani, Ichiro Mizushima, Shigeru Kambayashi, Hirotaka Nishino, Masahiro Kashiwagi