Patents by Inventor Yuichiro Yamashita

Yuichiro Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230369374
    Abstract: Image sensor structures are provided. In some embodiments, an image sensor structure is provided. The image sensor structure includes a substrate and a light-sensing region formed in the substrate and extending from the top surface to the bottom surface of the substrate. The image sensor structure further includes a first isolation structure extending from the top surface of the substrate to a middle portion of the substrate and a second isolation structure formed extending from the bottom surface of the substrate to the middle portion of the substrate and in contact with the first isolation structure. The image sensor structure further includes a gate structure overlapping the light-sensing region, the first isolation structure, and the second isolation structure and a cap layer overlapping the gate structure, the light-sensing region, the first isolation structure, and the second isolation structure in a top view.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 16, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuichiro YAMASHITA, Chun-Hao CHUANG, Hirofumi SUMI
  • Publication number: 20230335572
    Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a semiconductor substrate having sidewalls that form one or more trenches. The one or more trenches are disposed along opposing sides of a photodiode and vertically extend from an upper surface of the semiconductor substrate to within the semiconductor substrate. A doped region is arranged along the upper surface of the semiconductor substrate and along opposing sides of the photodiode. A first dielectric lines the sidewalls of the semiconductor substrate and the upper surface of the semiconductor substrate. A second dielectric lines sidewalls and an upper surface of the first dielectric. The doped region has a width laterally between a side of the photodiode and a side of the first dielectric. The width of the doped region varyies at different heights along the side of the photodiode.
    Type: Application
    Filed: June 16, 2023
    Publication date: October 19, 2023
    Inventors: Chun-Yuan Chen, Ching-Chun Wang, Dun-Nian Yaung, Hsiao-Hui Tseng, Jhy-Jyi Sze, Shyh-Fann Ting, Tzu-Jui Wang, Yen-Ting Chiang, Yu-Jen Wang, Yuichiro Yamashita
  • Patent number: 11776983
    Abstract: Image sensor structures are provided. The image sensor structure includes a substrate and a light-sensing region formed in the substrate. The image sensor structure further includes a first isolation structure surrounding the light sensing region and having an opening region in a top view and a second isolation structure formed in the substrate. In addition, the second isolation structure surrounds the light-sensing region and vertically overlaps both the opening region and the first isolation structure. The image sensor structure further includes a first gate structure formed over the substrate and overlapping the opening region, the first isolation structure, and the second isolation structure.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: October 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yuichiro Yamashita, Chun-Hao Chuang, Hirofumi Sumi
  • Publication number: 20230261021
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a deep trench isolation (DTI) structure disposed in a substrate. A pixel region of the substrate is disposed within an inner perimeter of the DTI structure. A photodetector is disposed in the pixel region of the substrate. A gate electrode structure overlies, at least partially, the pixel region of the substrate. A first gate dielectric structure partially overlies the pixel region of the substrate. A second gate dielectric structure partially overlies the pixel region of the substrate. The gate electrode structure overlies both a portion of the first gate dielectric structure and a portion of the second gate dielectric structure. The first gate dielectric structure has a first thickness. The second gate dielectric structure has a second thickness that is greater than the first thickness.
    Type: Application
    Filed: May 23, 2022
    Publication date: August 17, 2023
    Inventors: Tzu-Jui Wang, Dun-Nian Yaung, Chen-Jong Wang, Ming-Chieh Hsu, Wei-Cheng Hsu, Yuichiro Yamashita
  • Patent number: 11728366
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an image sensor disposed within a substrate. The substrate has sidewalls and a horizontally extending surface defining one or more trenches extending from a first surface of the substrate to within the substrate. One or more isolation structures are arranged within the one or more trenches. A doped region is arranged within the substrate laterally between sidewalls of the one or more isolation structures and the image sensor and vertically between the image sensor and the first surface of the substrate. The doped region has a higher concentration of a first dopant type than an abutting part of the substrate that extends along opposing sides of the image sensor.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yuan Chen, Ching-Chun Wang, Dun-Nian Yaung, Hsiao-Hui Tseng, Jhy-Jyi Sze, Shyh-Fann Ting, Tzu-Jui Wang, Yen-Ting Chiang, Yu-Jen Wang, Yuichiro Yamashita
  • Patent number: 11600650
    Abstract: In a photoelectric conversion apparatus including charge storing portions in its imaging region, isolation regions for the charge storing portions include first isolation portion each having a PN junction, and second isolation portions each having an insulator. A second isolation portion is arranged between a charge storing portion and at least a part of a plurality of transistors.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: March 7, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Masahiro Kobayashi, Yuichiro Yamashita
  • Publication number: 20220406823
    Abstract: The present disclosure relates to an image sensor including a pixel along a substrate. The pixel includes a first semiconductor region having a first doping type. A second semiconductor region is directly over the first semiconductor region. The second semiconductor region has a second doping type opposite the first doping type and meets the first semiconductor region at a p-n junction. A ring-shaped third semiconductor region laterally surrounds the first and second semiconductor regions. The ring-shaped third semiconductor region has the first doping type. A ring-shaped fourth semiconductor region laterally surrounds the ring-shaped third semiconductor region. The ring-shaped fourth semiconductor region has the second doping type. A ring-shaped fifth semiconductor region is directly over the ring-shaped third semiconductor region and has the second doping type.
    Type: Application
    Filed: June 16, 2021
    Publication date: December 22, 2022
    Inventors: Tzu-Jui Wang, Yuichiro Yamashita
  • Publication number: 20220278161
    Abstract: The present disclosure describes a semiconductor device that includes a first die bonded to a second die with interconnect structures in the first die. The first die includes a photodiode having first and second electrodes on a first side of a first dielectric layer, and first, second, and third interconnect structures in the first dielectric layer. The first and second interconnect structures are connected to the first and second electrodes, respectively. The second electrode has a polarity opposite to the first electrode. The second and third interconnect structures extend to a second side opposite to the first side of the first dielectric layer. The second die includes a second dielectric layer and a fourth interconnect structure in the second dielectric layer. The second dielectric layer is bonded to the second side of the first dielectric layer. The fourth interconnect structure connects the second and third interconnect structures.
    Type: Application
    Filed: December 30, 2021
    Publication date: September 1, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Chin HUANG, Tzu-Jui WANG, Hua-Mao CHEN, Chin-Chia KUO, Yuichiro YAMASHITA
  • Patent number: 11348953
    Abstract: An image sensor includes a semiconductor substrate having first and second faces. The sensor includes a plurality of pixel groups each including pixels, each pixel having a photoelectric converter and a wiring pattern, the converter including a region whose major carriers are the same with charges to be accumulated in the photoelectric converter. The sensor also includes a microlenses which are located so that one microlens is arranged for each pixel group. The wiring patterns are located at a side of the first face, and the plurality of microlenses are located at a side of the second face. Light-incidence faces of the regions of the photoelectric converters of each pixel group are arranged along the second face such that the light-incidence faces are apart from each other in a direction along the second face.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: May 31, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masaaki Minowa, Hidekazu Takahashi, Yuichiro Yamashita, Akira Okita
  • Patent number: 11264525
    Abstract: A single photon avalanche diode (SPAT) image sensor is disclosed. The SPAT) image sensor include: a substrate of a first conductivity type, the substrate having a front surface and a back surface; a deep trench isolation (DTI) extending from the front surface toward the back surface of the substrate, the DTI having a first surface and a second surface opposite to the first surface, the first surface being level with the front surface of the substrate; an epitaxial layer of a second conductivity type opposite to the first conductivity type, the epitaxial layer surrounding sidewalls and the second surface of the DTI; and an implant region of the first conductivity type extending from the front surface to the back surface of the substrate. An associated method for fabricating the SPAD image sensor is also disclosed.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tzu-Jui Wang, Jhy-Jyi Sze, Yuichiro Yamashita, Kuo-Chin Huang
  • Publication number: 20220059583
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an image sensor disposed within a substrate. The substrate has sidewalls and a horizontally extending surface defining one or more trenches extending from a first surface of the substrate to within the substrate. One or more isolation structures are arranged within the one or more trenches. A doped region is arranged within the substrate laterally between sidewalls of the one or more isolation structures and the image sensor and vertically between the image sensor and the first surface of the substrate. The doped region has a higher concentration of a first dopant type than an abutting part of the substrate that extends along opposing sides of the image sensor.
    Type: Application
    Filed: November 5, 2021
    Publication date: February 24, 2022
    Inventors: Chun-Yuan Chen, Ching-Chun Wang, Dun-Nian Yaung, Hsiao-Hui Tseng, Jhy-Jyi Sze, Shyh-Fann Ting, Tzu-Jui Wang, Yen-Ting Chiang, Yu-Jen Wang, Yuichiro Yamashita
  • Patent number: 11239383
    Abstract: A single photon avalanche diode (SPAD) image sensor is disclosed. The SPAD image sensor includes: a substrate having a front surface and a back surface; wherein the substrate includes a sensing region, and the sensing region includes: a common node heavily doped with dopants of a first conductivity type, the common node being within the substrate and abutting the back surface of the substrate; a sensing node heavily doped with dopants of a second conductivity type opposite to the first conductivity type, the sensing node being within the substrate and abutting the front surface of the substrate; and a first layer doped with dopants of the first conductivity type between the common node and the sensing node.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: February 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Yuichiro Yamashita
  • Patent number: 11227889
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an image sensing element disposed within a semiconductor substrate. One or more isolation structures are arranged within one or more trenches disposed along a first surface of the semiconductor substrate. The one or more isolation structures are separated from opposing sides of the image sensing element by non-zero distances. The one or more trenches are defined by sidewalls and a horizontally extending surface of the semiconductor substrate. A doped region is laterally arranged between the sidewalls of the semiconductor substrate defining the one or more trenches and is vertically arranged between the image sensing element and the first surface of the semiconductor substrate.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: January 18, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Yuan Chen, Ching-Chun Wang, Dun-Nian Yaung, Hsiao-Hui Tseng, Jhy-Jyi Sze, Shyh-Fann Ting, Tzu-Jui Wang, Yen-Ting Chiang, Yu-Jen Wang, Yuichiro Yamashita
  • Publication number: 20210366955
    Abstract: In a photoelectric conversion apparatus including charge storing portions in its imaging region, isolation regions for the charge storing portions include first isolation portion each having a PN junction, and second isolation portions each having an insulator. A second isolation portion is arranged between a charge storing portion and at least a part of a plurality of transistors.
    Type: Application
    Filed: August 4, 2021
    Publication date: November 25, 2021
    Inventors: Masahiro Kobayashi, Yuichiro Yamashita
  • Patent number: 11127774
    Abstract: An image sensor is disclosed. The image sensor includes: a common node heavily doped with dopants of a first conductivity type, the common node being within the substrate and abutting the front surface of the substrate; and a sensing node heavily doped with dopants of a second conductivity type opposite to the first conductivity type, the sensing node being within the substrate and abutting the front surface of the substrate; an interconnect structure, wherein the front surface of the substrate faces the interconnect structure; a distributed Bragg reflector (DBR) between the front surface of the substrate and the interconnect structure; a first contact plug passing through the DBR and coupling the common node to the interconnect structure; and a second contact plug passing through the DBR and coupling the sensing node to the interconnect structure.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: September 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Yuichiro Yamashita
  • Patent number: 11127770
    Abstract: An imaging apparatus includes a plurality of pixels, a signal holding unit, first and second control electrodes. Each of the plurality of pixels includes a photoelectric conversion unit, and an amplification element to amplify signals based on signal charges generated by the photoelectric conversion unit, in which the plurality of pixels output signals for performing a phase contrast detection type of focal point detection. The signal holding unit is in an electrical pathway between an output node of the photoelectric conversion unit and an input node of the amplification element, in which signals for performing the phase contrast detection type of focal point detection are held. The first control electrode is configured to transfer a signal of the photoelectric conversion unit to the signal holding unit. The second control electrode is configured to transfer a signal for performing the phase difference detection type of focal point detection.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: September 21, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yuichiro Yamashita, Masahiro Kobayashi, Itsutaku Sano, Takeshi Kojima
  • Patent number: 11114487
    Abstract: In a photoelectric conversion apparatus including charge storing portions in its imaging region, isolation regions for the charge storing portions include first isolation portion each having a PN junction, and second isolation portions each having an insulator. A second isolation portion is arranged between a charge storing portion and at least a part of a plurality of transistors.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: September 7, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Masahiro Kobayashi, Yuichiro Yamashita
  • Publication number: 20210225908
    Abstract: Image sensor structures are provided. The image sensor structure includes a substrate and a light-sensing region formed in the substrate. The image sensor structure further includes a first isolation structure surrounding the light sensing region and having an opening region in a top view and a second isolation structure formed in the substrate. In addition, the second isolation structure surrounds the light-sensing region and vertically overlaps both the opening region and the first isolation structure. The image sensor structure further includes a first gate structure formed over the substrate and overlapping the opening region, the first isolation structure, and the second isolation structure.
    Type: Application
    Filed: April 7, 2021
    Publication date: July 22, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuichiro YAMASHITA, Chun-Hao CHUANG, Hirofumi SUMI
  • Patent number: 11063080
    Abstract: An image sensor is disclosed. The image sensor includes an epitaxial layer, a plurality of plug structures and an interconnect structure. Wherein the plurality of plug structures are formed in the epitaxial layer, and each plug structure has doped sidewalls, the epitaxial layer and the doped sidewalk form a plurality of photodiodes, the plurality of plug structures are used to separate adjacent photodiodes, and the epitaxial layer and the doped sidewalls are coupled to the interconnect structure via the plug structures. An associated method of fabricating the image sensor is also disclosed. The method includes: providing a substrate having a first-type doped epitaxial substrate layer on a second-type doped epitaxial substrate layer; forming a plurality of isolation trenches in the first-type doped epitaxial substrate layer; forming a second-type doped region along sidewalk and bottoms of the plurality of isolation trenches; and filling the plurality of isolation trenches by depositing metal.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: July 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Alexander Kalnitsky, Jhy-Jyi Sze, Dun-Nian Yaung, Chen-Jong Wang, Yimin Huang, Yuichiro Yamashita
  • Patent number: 10991747
    Abstract: Image sensor structures are provided. The image sensor structure includes a substrate having a front side and a backside and a light-sensing region formed in the substrate. The image sensor structure further includes a front side isolation structure surrounding the light sensing region and having an opening region in a top view and a backside isolation structure formed at the backside of the substrate and encompassing the light-sensing region and vertically overlapping the opening region. The image sensor structure further includes a first gate structure formed over the front side of the substrate and overlapping the opening region and the front side isolation structure and a storage node in the substrate adjacent to the first gate structure. In addition, the storage node extends into the opening region.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yuichiro Yamashita, Chun-Hao Chuang, Hirofumi Sumi