Abstract: Characteristics of a high electron mobility transistor are improved. A stack having an n-type contact layer (n-type AlGaN layer), an electron supply layer (undoped AlGaN layer), and a channel layer (undoped GaN layer) is formed in a growth mode over a Ga plane parallel with a [0001] crystal axis direction. Then, after turning the stack upside down so that the n-type contact layer (n-type AlGaN layer) is situated to the upper surface and forming a trench, a gate electrode is formed by way of a gate insulation film. By stacking the channel layer (undoped GaN layer) and the electron supply layer (undoped AlGaN layer) successively in a [000-1] direction, (1) normally off operation and (2) increase of withstanding voltage can easily be compatible with each other.

Abstract: A field effect transistor includes a substrate and a semiconductor layer provided on the substrate, wherein the semiconductor layer includes a lower barrier layer provided on the substrate, Ga-face grown, lattice relaxed, and having a composition In1?zAlzN (0?z?1), a channel layer having a composition of: AlxGa1?xN (0?x?1) or InyGa1?yN (0?y?1). Or GaN provided on and lattice-matched to the lower barrier layer, a source electrode and a drain electrode having ohmic contact to an upper part of the semiconductor layers, disposed spaced to each other, and a gate electrode arranged via a gate insulating film in a region lying between the source electrode and the drain electrode.

Abstract: Provided is a semiconductor device in which the trade-off between the withstand voltage and the on-resistance is improved and the performance is increased. A semiconductor device comprises a substrate 1, a first n-type semiconductor layer 21?, a second n-type semiconductor layer 23, a p-type semiconductor layer 24, and a third n-type semiconductor layer 25?, wherein the first n-type semiconductor layer 21?, the second n-type semiconductor layer 23, the p-type semiconductor layer 24, and the third n-type semiconductor layer 25? are laminated at the upper side of the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 21? and the source electrode 12 is in ohmic-contact with the third n-type semiconductor layer 25?.

Abstract: An organopolysiloxane emulsion composition produced by the emulsion polymerization of an emulsion that comprises (A) an organopolysiloxane containing a silanol group or an organooxy group, (B) a nonionic surfactant represented by formula (2): R2O(EO)a(PO)bR3 (wherein R2 represents an alkyl group or R4(CO)—; R4 represents an alkyl group; R3 represents an alkyl group or R5(CO)—; R5 represents an alkyl group; EO represents an ethylene oxide group; PO represents an alkylene oxide group; and a and b independently represent 0 to 100, wherein a+b >0 and the sequence of EO and PO may be random or in the form of a block) and (C) a surfactant other than the component (B), and may additionally comprise (D) a polymerization catalyst and (E) water if required. According to the present invention, it becomes possible to produce an extremely stable organopolysiloxane emulsion composition without inhibiting polymerization during the emulsion polymerization of an organopolysiloxane having condensation reactivity.

Abstract: Provided is an imaging control device including a result receiving unit configured to receive an example image selected by an image processing device used for image processing using image information, the image information being information regarding an image captured by an imaging unit used for image capturing, a selection result transmitting unit configured to transmit information regarding the example image received by the result receiving unit to the image processing device, a setting receiving unit configured to receive setting information generated by the image processing device based on the example image transmitted from the selection result transmitting unit, the setting information indicating a setting condition when image capturing is performed like the example image, and a setting change unit configured to change an imaging setting of the imaging unit using the setting information received by the setting receiving unit.

Abstract: Provided is an image processing device including a disparity detector configured to receive a plurality of 3D images and detect disparity of each of the 3D images, a disparity analyzer configured to generate statistical information about disparity of each 3D image using the disparity of each 3D image detected by the disparity detector, and a disparity controller configured to convert the disparity using the statistical information about disparity of each 3D image generated by the disparity analyzer in such a manner that the 3D images are not overlapped so that a range of the disparity is within a predetermined range.

Abstract: A field effect transistor includes a substrate and a semiconductor layer provided on the substrate, wherein the semiconductor layer includes a lower barrier layer provided on the substrate, Ga-face grown, lattice relaxed, and having a composition In1-zAlzN (0?z?1), a channel layer having a composition of: AlxGa1-xN (0?x?1) or InyGa1-yN (0?y?1). Or GaN provided on and lattice-matched to the lower barrier layer, a source electrode and a drain electrode having ohmic contact to an upper part of the semiconductor layers, disposed spaced to each other, and a gate electrode arranged via a gate insulating film in a region lying between the source electrode and the drain electrode.

Abstract: The present invention provides a field effect transistor which can achieve both of a high threshold voltage and a low on-state resistance, a method for producing the same, and an electronic device. In the field effect transistor, each of a buffer layer 112, a channel layer 113, a barrier layer 114, and a spacer layer 115 is formed of a group-III nitride semiconductor, and each of the upper surfaces thereof is a group-III atomic plane that is perpendicular to a (0001) crystal axis. The lattice-relaxed buffer layer 112, the channel layer 113 having a compressive strain, and the barrier layer 114 having a tensile strain, and the spacer layer 115 having a compressive strain are laminated on a substrate 100 in this order. The gate insulating film 14 is arranged on the spacer layer 115. The gate electrode 15 is arranged on the gate insulating film 14. The source electrode 161 and the drain electrode 162 are electrically connected to the channel layer 113 directly or via another component.

Abstract: A method for producing an organopolysiloxane emulsion composition, which enables the organopolysiloxane to be formed with a high viscosity in a short period of time, and suppresses the amount of octamethylcyclotetrasiloxane (D4) to not more than 3,000 ppm. Specifically, a method for producing an organopolysiloxane emulsion which includes emulsifying a mixture containing an organopolysiloxane represented by formula: HO(R12SiO)nH and having a D4 content of not more than 1,000 ppm, a nonionic surfactant, an anionic surfactant, and water, and subjecting the obtained emulsion composition to emulsion polymerization, thus preparing the emulsion composition.

Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).

Abstract: In a high electron mobility transistor, with a normally-off operation maintained, on-resistance can be sufficiently reduced, so that the performance of a semiconductor device including the high electron mobility transistor is improved. Between a channel layer and an electron supply layer, a spacer layer whose band gap is larger than the band gap of the electron supply layer is provided. Thereby, due to the fact that the band gap of the spacer layer is large, a high potential barrier (electron barrier) is formed in the vicinity of an interface between the channel and the electron supply layer.

Abstract: The present technology is related to an image processing device and image processing method that enables the generating of 3D images that can be viewed safely and comfortably. The communication unit acquires encoded data of 3D images, and the 3D image bitstream that includes at least the disparity information representing the disparity of these 3D images. The CPU specifies the playback timing of the 3D images. Based on the disparity information, the CPU determines the re-encoding section, which is the section of a front stream and back stream where adjustment of the disparity is needed, so that the difference between the disparity of 3D images of which the timings of playback are consecutive is at or below a predetermined threshold. The editing unit adjusts the disparity of the image data in the re-encoding section. The present technology is applicable, for example, to an editing device that edits 3D images.

Abstract: There is provided an image processing apparatus that includes a move detecting unit that detects a move of a subject contained in a moving image from plural frame images, based on an image signal that indicates the moving image including the frame image and delay time information that indicates a delay time of an image pickup, and a correcting unit that corrects the image signal, based on the image signal and move information that indicates a move of a detected subject.

Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).

Abstract: The present technology is related to an image processing device and image processing method that enables the generating of 3D images that can be viewed safely and comfortably. The communication unit acquires encoded data of 3D images, and the 3D image bitstream that includes at least the disparity information representing the disparity of these 3D images. The CPU specifies the playback timing of the 3D images. Based on the disparity information, the CPU determines the re-encoding section, which is the section of a front stream and back stream where adjustment of the disparity is needed, so that the difference between the disparity of 3D images of which the timings of playback are consecutive is at or below a predetermined threshold. The editing unit adjusts the disparity of the image data in the re-encoding section. The present technology is applicable, for example, to an editing device that edits 3D images.

Abstract: A high electron mobility transistor having a channel layer, electron supply layer, source electrode, and drain electrode is included so as to have a cap layer formed on the electron supply layer between the source and drain electrodes and having an inclined side surface, an insulating film having an opening portion on the upper surface of the cap layer and covering the side surface thereof, and a gate electrode is formed in the opening portion and extending, via the insulating film, over the side surface of the cap layer on the drain electrode side. The gate electrode having an overhang on the drain electrode side can reduce the peak electric field.

Abstract: A semiconductor device includes semiconductor layers, an anode electrode, and a cathode electrode. The semiconductor layers include a composition change layer, the anode electrode is electrically connected to one of principal surfaces of the composition change layer through a formation of a Schottky junction between the anode electrode and a part of the semiconductor layers, the cathode electrode is electrically connected to the other of the principal surfaces of the composition change layer through a formation of a junction between the cathode electrode and another part of the semiconductor layers, the anode electrode and the cathode electrode are capable of applying a voltage to the composition change layer in a direction perpendicular to the principal surface.

Abstract: A bipolar transistor is provided with an emitter layer, a base layer and a collector layer. The emitter layer is formed above a substrate and is an n-type conductive layer including a first nitride semiconductor. The base layer is formed on the emitter layer and is a p-type conductive including a second nitride semiconductor. The collector layer is formed on the base layer and includes a third nitride semiconductor. The collector layer, the base layer and the emitter layer are formed such that a crystal growth direction to the substrate surface is parallel to a substrate direction of [000-1]. The third nitride semiconductor contains InycAlxcGa1-xc-ycN (0•xc•1, 0•yc•1, 0<xc+yc•1). The a-axis length on the side of a surface in the third nitride semiconductor is shorter than the a-axis length on the side of the substrate.

Abstract: There is provided an image processing device including a converter configured to obtain, prior to performing an encoding process, image drawing information of an image capable of using upon encoding and to convert the obtained image drawing information into a parameter for encoding, and an encoding processor configured to perform the encoding process by changing contents of the encoding process according to the parameter for encoding converted by the converter.

Abstract: A field effect transistor includes a substrate and a semiconductor layer provided on the substrate, wherein the semiconductor layer includes a lower barrier layer provided on the substrate, Ga-face grown, lattice relaxed, and having a composition In1-zAlzN (0?z?1), a channel layer having a composition of: AlxGa1-xN (0?x?1) or InyGa1-yN (0?y?1). Or GaN provided on and lattice-matched to the lower barrier layer, a source electrode and a drain electrode having ohmic contact to an upper part of the semiconductor layers, disposed spaced to each other, and a gate electrode arranged via a gate insulating film in a region lying between the source electrode and the drain electrode.