Patents by Inventor Yuji Ando
Yuji Ando has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9540541Abstract: An organopolysiloxane emulsion composition produced by the emulsion polymerization of an emulsion that comprises (A) an organopolysiloxane containing a silanol group or an organooxy group, (B) a nonionic surfactant represented by formula (2): R2O(EO)a(PO)bR3 (wherein R2 represents an alkyl group or R4(CO)—; R4 represents an alkyl group; R3 represents an alkyl group or R5(CO)—; R5 represents an alkyl group; EO represents an ethylene oxide group; PO represents an alkylene oxide group; and a and b independently represent 0 to 100, wherein a+b>0 and the sequence of EO and PO may be random or in the form of a block) and (C) a surfactant other than the component (B), and may additionally comprise (D) a polymerization catalyst and (E) water if required. According to the present invention, it becomes possible to produce an extremely stable organopolysiloxane emulsion composition without inhibiting polymerization during the emulsion polymerization of an organopolysiloxane having condensation reactivity.Type: GrantFiled: March 28, 2013Date of Patent: January 10, 2017Assignee: SHIN-ETSU CHEMICAL CO., LTD.Inventor: Yuji Ando
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Patent number: 9530879Abstract: A semiconductor device including a field effect transistor including a substrate, a lower barrier layer provided on the substrate, a channel layer provided on the lower barrier layer, an electron supplying layer provided on the channel layer, a source electrode and a drain electrode provided on the electron layer, and a gate electrode provided between the source electrode and the drain electrode. The lower barrier layer includes a composition of In1-zAlzN (0?z?1). The channel layer includes a composition of AlxGa1-xN (0?x?1). A recess is provided in a region between the source electrode and the drain electrode, wherein the recess goes through the electron supplying layer to a depth that exposes the channel layer, and the gate electrode is disposed on a gate insulating film that covers a bottom surface and an inner wall surface of the recess.Type: GrantFiled: November 20, 2015Date of Patent: December 27, 2016Assignee: Renesas Electronics CorporationInventors: Yasuhiro Okamoto, Yuji Ando, Tatsuo Nakayama, Takashi Inoue, Kazuki Ota
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Publication number: 20160165246Abstract: The present disclosure relates to an image processing device and a method thereof which enable a high image quality process with higher efficiency. A decoding section outputs, in addition to a decoded image, hierarchical block split information of a CU, a PU, and a TU to an image processing section as motion vector information and image split information that are encoded information included in a bit stream used in decoding. The image processing section specifies a dynamic body area from the decoded image supplied from the decoding section using the hierarchical block split information that is the encoded information from the decoding section, and performs a high image quality process. The present disclosure can be applied to, for example, an image processing device which performs a high image quality process on a decoded image that has been decoded.Type: ApplicationFiled: July 8, 2014Publication date: June 9, 2016Inventors: TAKEFUMI NAGUMO, YUJI ANDO, NOBUAKI IZUMI
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Publication number: 20160079409Abstract: A semiconductor device including a field effect transistor including a substrate, a lower barrier layer provided on the substrate, a channel layer provided on the lower barrier layer, an electron supplying layer provided on the channel layer, a source electrode and a drain electrode provided on the electron layer, and a gate electrode provided between the source electrode and the drain electrode. The lower barrier layer includes a composition of In1-zAlzN (0?z?1). The channel layer includes a composition of AlxGa1-xN (0?x?1). A recess is provided in a region between the source electrode and the drain electrode, wherein the recess goes through the electron supplying layer to a depth that exposes the channel layer, and the gate electrode is disposed on a gate insulating film that covers a bottom surface and an inner wall surface of the recess.Type: ApplicationFiled: November 20, 2015Publication date: March 17, 2016Applicant: Renesas Electronics CorporationInventors: Yasuhiro OKAMOTO, Yuji ANDO, Tatsuo NAKAYAMA, Takashi INOUE, Kazuki OTA
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Patent number: 9231096Abstract: A field effect transistor includes a substrate and a semiconductor layer provided on the substrate, wherein the semiconductor layer includes a lower barrier layer provided on the substrate, Ga-face grown, lattice relaxed, and having a composition In1?zAlzN (0?z?1), a channel layer having a composition of: AlxGa1?xN (0?x?1) or InyGa1?yN (0?y?1). Or GaN provided on and lattice-matched to the lower barrier layer, a source electrode and a drain electrode having ohmic contact to an upper part of the semiconductor layers, disposed spaced to each other, and a gate electrode arranged via a gate insulating film in a region lying between the source electrode and the drain electrode.Type: GrantFiled: November 21, 2014Date of Patent: January 5, 2016Assignee: Renesas Electronics CorporationInventors: Yasuhiro Okamoto, Yuji Ando, Tatsuo Nakayama, Takashi Inoue, Kazuki Ota
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Publication number: 20150290091Abstract: Provided is a cosmetic preparation superior in stability and feel. The cosmetic preparation contains an (a) organopolysiloxane emulsion in an amount of not smaller than 0.1% by mass. This organopolysiloxane emulsion is obtained through emulsion polymerization and contains octamethylcyclotetrasiloxane in an amount of not larger than 1,000 ppm by mass.Type: ApplicationFiled: November 28, 2013Publication date: October 15, 2015Applicant: Shin-Etsu Chemical Co., Ltd.Inventors: Yuji Ando, Shinji Irifune
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Publication number: 20150271500Abstract: An information processing apparatus includes: a storage unit configured to store information on a plurality of encoders; and a control unit configured to be capable of transmitting a first instruction signal for instructing the plurality of encoders to encode input video data under first encoding conditions different for each of the plurality of encoders, and obtaining, if an image quality of the video data encoded by the plurality of encoders does not satisfy a predetermined criteria, predetermined information associated with the image quality from the encoded video data and transmitting, based on the predetermined information, a second instruction signal for instructing to encode the input video data under a second encoding condition different from the first encoding conditions to at least one encoder of the plurality of encoders.Type: ApplicationFiled: March 12, 2015Publication date: September 24, 2015Inventors: MASAKAZU KOUNO, YUJI ANDO
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Patent number: 9072666Abstract: A method for producing an organopolysiloxane emulsion composition, which enables the organopolysiloxane to be formed with a high viscosity in a short period of time, and suppresses the amount of octamethylcyclotetrasiloxane (D4) to not more than 3,000 ppm. Specifically, a method for producing an organopolysiloxane emulsion which includes emulsifying a mixture containing an organopolysiloxane represented by formula: HO(R12SiO)nH and having a D4 content of not more than 1,000 ppm, a nonionic surfactant, an anionic surfactant, and water, and subjecting the obtained emulsion composition to emulsion polymerization, thus preparing the emulsion composition.Type: GrantFiled: January 24, 2013Date of Patent: July 7, 2015Assignee: Shin-Etsu Chemical Co., Ltd.Inventor: Yuji Ando
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Publication number: 20150084104Abstract: Characteristics of a high electron mobility transistor are improved. A stack having an n-type contact layer (n-type AlGaN layer), an electron supply layer (undoped AlGaN layer), and a channel layer (undoped GaN layer) is formed in a growth mode over a Ga plane parallel with a [0001] crystal axis direction. Then, after turning the stack upside down so that the n-type contact layer (n-type AlGaN layer) is situated to the upper surface and forming a trench, a gate electrode is formed by way of a gate insulation film. By stacking the channel layer (undoped GaN layer) and the electron supply layer (undoped AlGaN layer) successively in a [000-1] direction, (1) normally off operation and (2) increase of withstanding voltage can easily be compatible with each other.Type: ApplicationFiled: September 2, 2014Publication date: March 26, 2015Applicant: Renesas Electronics CorporationInventor: Yuji ANDO
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Publication number: 20150076511Abstract: A field effect transistor includes a substrate and a semiconductor layer provided on the substrate, wherein the semiconductor layer includes a lower barrier layer provided on the substrate, Ga-face grown, lattice relaxed, and having a composition In1?zAlzN (0?z?1), a channel layer having a composition of: AlxGa1?xN (0?x?1) or InyGa1?yN (0?y?1). Or GaN provided on and lattice-matched to the lower barrier layer, a source electrode and a drain electrode having ohmic contact to an upper part of the semiconductor layers, disposed spaced to each other, and a gate electrode arranged via a gate insulating film in a region lying between the source electrode and the drain electrode.Type: ApplicationFiled: November 21, 2014Publication date: March 19, 2015Applicant: Renesas Electronics CorporationInventors: Yasuhiro OKAMOTO, Yuji ANDO, Tatsuo NAKAYAMA, Takashi INOUE, Kazuki OTA
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Patent number: 8981434Abstract: Provided is a semiconductor device in which the trade-off between the withstand voltage and the on-resistance is improved and the performance is increased. A semiconductor device comprises a substrate 1, a first n-type semiconductor layer 21?, a second n-type semiconductor layer 23, a p-type semiconductor layer 24, and a third n-type semiconductor layer 25?, wherein the first n-type semiconductor layer 21?, the second n-type semiconductor layer 23, the p-type semiconductor layer 24, and the third n-type semiconductor layer 25? are laminated at the upper side of the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 21? and the source electrode 12 is in ohmic-contact with the third n-type semiconductor layer 25?.Type: GrantFiled: June 23, 2010Date of Patent: March 17, 2015Assignee: Renesas Electronics CorporationInventors: Hironobu Miyamoto, Yasuhiro Okamoto, Yuji Ando, Tatsuo Nakayama, Takashi Inoue, Kazuki Ota, Kazuomi Endo
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Publication number: 20150036003Abstract: Provided is an imaging control device including a result receiving unit configured to receive an example image selected by an image processing device used for image processing using image information, the image information being information regarding an image captured by an imaging unit used for image capturing, a selection result transmitting unit configured to transmit information regarding the example image received by the result receiving unit to the image processing device, a setting receiving unit configured to receive setting information generated by the image processing device based on the example image transmitted from the selection result transmitting unit, the setting information indicating a setting condition when image capturing is performed like the example image, and a setting change unit configured to change an imaging setting of the imaging unit using the setting information received by the setting receiving unit.Type: ApplicationFiled: January 11, 2013Publication date: February 5, 2015Inventors: Hironari Sakurai, Jun Kimura, Yuji Ando, Keisuke Yamaoka, Takefumi Nagumo, Masashi Eshima
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Publication number: 20150037272Abstract: An organopolysiloxane emulsion composition produced by the emulsion polymerization of an emulsion that comprises (A) an organopolysiloxane containing a silanol group or an organooxy group, (B) a nonionic surfactant represented by formula (2): R2O(EO)a(PO)bR3 (wherein R2 represents an alkyl group or R4(CO)—; R4 represents an alkyl group; R3 represents an alkyl group or R5(CO)—; R5 represents an alkyl group; EO represents an ethylene oxide group; PO represents an alkylene oxide group; and a and b independently represent 0 to 100, wherein a+b >0 and the sequence of EO and PO may be random or in the form of a block) and (C) a surfactant other than the component (B), and may additionally comprise (D) a polymerization catalyst and (E) water if required. According to the present invention, it becomes possible to produce an extremely stable organopolysiloxane emulsion composition without inhibiting polymerization during the emulsion polymerization of an organopolysiloxane having condensation reactivity.Type: ApplicationFiled: March 28, 2013Publication date: February 5, 2015Inventor: Yuji Ando
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Publication number: 20150030235Abstract: Provided is an image processing device including a disparity detector configured to receive a plurality of 3D images and detect disparity of each of the 3D images, a disparity analyzer configured to generate statistical information about disparity of each 3D image using the disparity of each 3D image detected by the disparity detector, and a disparity controller configured to convert the disparity using the statistical information about disparity of each 3D image generated by the disparity analyzer in such a manner that the 3D images are not overlapped so that a range of the disparity is within a predetermined range.Type: ApplicationFiled: December 25, 2012Publication date: January 29, 2015Applicant: Sony CorporationInventors: Kiyoto Someya, Kohei Miyamoto, Nobuaki Izumi, Satoru Kuma, Yuji Ando
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Patent number: 8928038Abstract: A field effect transistor includes a substrate and a semiconductor layer provided on the substrate, wherein the semiconductor layer includes a lower barrier layer provided on the substrate, Ga-face grown, lattice relaxed, and having a composition In1-zAlzN (0?z?1), a channel layer having a composition of: AlxGa1-xN (0?x?1) or InyGa1-yN (0?y?1). Or GaN provided on and lattice-matched to the lower barrier layer, a source electrode and a drain electrode having ohmic contact to an upper part of the semiconductor layers, disposed spaced to each other, and a gate electrode arranged via a gate insulating film in a region lying between the source electrode and the drain electrode.Type: GrantFiled: May 15, 2012Date of Patent: January 6, 2015Assignee: Renesas Electronics CorporationInventors: Yasuhiro Okamoto, Yuji Ando, Tatsuo Nakayama, Takashi Inoue, Kazuki Ota
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Patent number: 8921894Abstract: The present invention provides a field effect transistor which can achieve both of a high threshold voltage and a low on-state resistance, a method for producing the same, and an electronic device. In the field effect transistor, each of a buffer layer 112, a channel layer 113, a barrier layer 114, and a spacer layer 115 is formed of a group-III nitride semiconductor, and each of the upper surfaces thereof is a group-III atomic plane that is perpendicular to a (0001) crystal axis. The lattice-relaxed buffer layer 112, the channel layer 113 having a compressive strain, and the barrier layer 114 having a tensile strain, and the spacer layer 115 having a compressive strain are laminated on a substrate 100 in this order. The gate insulating film 14 is arranged on the spacer layer 115. The gate electrode 15 is arranged on the gate insulating film 14. The source electrode 161 and the drain electrode 162 are electrically connected to the channel layer 113 directly or via another component.Type: GrantFiled: December 15, 2010Date of Patent: December 30, 2014Assignee: NEC CorporationInventors: Yuji Ando, Takashi Inoue, Kazuki Ota, Yasuhiro Okamoto, Tatsuo Nakayama, Kazuomi Endo
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Publication number: 20140378553Abstract: A method for producing an organopolysiloxane emulsion composition, which enables the organopolysiloxane to be formed with a high viscosity in a short period of time, and suppresses the amount of octamethylcyclotetrasiloxane (D4) to not more than 3,000 ppm. Specifically, a method for producing an organopolysiloxane emulsion which includes emulsifying a mixture containing an organopolysiloxane represented by formula: HO(R12SiO)nH and having a D4 content of not more than 1,000 ppm, a nonionic surfactant, an anionic surfactant, and water, and subjecting the obtained emulsion composition to emulsion polymerization, thus preparing the emulsion composition.Type: ApplicationFiled: January 24, 2013Publication date: December 25, 2014Applicant: Shin-Etsu Chemical Co., Ltd.Inventor: Yuji Ando
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Publication number: 20140367743Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).Type: ApplicationFiled: August 27, 2014Publication date: December 18, 2014Inventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto
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Patent number: 8907349Abstract: In a high electron mobility transistor, with a normally-off operation maintained, on-resistance can be sufficiently reduced, so that the performance of a semiconductor device including the high electron mobility transistor is improved. Between a channel layer and an electron supply layer, a spacer layer whose band gap is larger than the band gap of the electron supply layer is provided. Thereby, due to the fact that the band gap of the spacer layer is large, a high potential barrier (electron barrier) is formed in the vicinity of an interface between the channel and the electron supply layer.Type: GrantFiled: April 29, 2013Date of Patent: December 9, 2014Assignee: Renesas Electronics CorporationInventors: Yuji Ando, Kazuki Ota
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Publication number: 20140334537Abstract: The present technology is related to an image processing device and image processing method that enables the generating of 3D images that can be viewed safely and comfortably. The communication unit acquires encoded data of 3D images, and the 3D image bitstream that includes at least the disparity information representing the disparity of these 3D images. The CPU specifies the playback timing of the 3D images. Based on the disparity information, the CPU determines the re-encoding section, which is the section of a front stream and back stream where adjustment of the disparity is needed, so that the difference between the disparity of 3D images of which the timings of playback are consecutive is at or below a predetermined threshold. The editing unit adjusts the disparity of the image data in the re-encoding section. The present technology is applicable, for example, to an editing device that edits 3D images.Type: ApplicationFiled: July 29, 2014Publication date: November 13, 2014Applicant: Sony CorporationInventors: Yuji Ando, Masami Ogata