Patents by Inventor Yuji Egi

Yuji Egi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210320193
    Abstract: A semiconductor device having favorable electrical characteristics is provided. A manufacturing method of the semiconductor device includes the steps of forming a first oxide over a substrate; depositing a first insulator over the first oxide; forming an opening reaching the first oxide in the first insulator; depositing a first oxide film in contact with the first oxide and the first insulator in the opening; depositing a first insulating film over the first oxide film by a PEALD method; depositing a first conductive film over the first insulating film; and removing part of the first oxide film, part of the first insulating film, and part of the first conductive film until a top surface of the first insulator is exposed to form a second oxide, a second insulator, and a first conductor. The deposition of the first insulating film is performed while the substrate is heated to higher than or equal to 300° C.
    Type: Application
    Filed: August 30, 2019
    Publication date: October 14, 2021
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Naoki OKUNO, Tetsuya KAKEHATA, Hiroki KOMAGATA, Yuji EGI
  • Publication number: 20210233769
    Abstract: A semiconductor device having favorable electrical characteristics is provided. A metal oxide is formed over a substrate by the steps of: introducing a first precursor into a chamber in which the substrate is provided; introducing a first oxidizer after the introduction of the first precursor; introducing a second precursor after the introduction of the first oxidizer; and introducing a second oxidizer after the introduction of the second precursor.
    Type: Application
    Filed: May 31, 2019
    Publication date: July 29, 2021
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Tetsuya KAKEHATA, Yuji EGI, Yasuhiro JINBO, Yujiro SAKURADA
  • Publication number: 20210184042
    Abstract: A transistor with stable electrical characteristics. A semiconductor device includes a first insulator over a substrate, a second insulator over the first insulator, an oxide semiconductor in contact with at least part of a top surface of the second insulator, a third insulator in contact with at least part of a top surface of the oxide semiconductor, a first conductor and a second conductor electrically connected to the oxide semiconductor, a fourth insulator over the third insulator, a third conductor which is over the fourth insulator and at least part of which is between the first conductor and the second conductor, and a fifth insulator over the third conductor. The first insulator contains a halogen element.
    Type: Application
    Filed: February 4, 2021
    Publication date: June 17, 2021
    Inventors: Tetsuhiro TANAKA, Mitsuhiro ICHIJO, Toshiya ENDO, Akihisa SHIMOMURA, Yuji EGI, Sachiaki TEZUKA, Shunpei YAMAZAKI
  • Patent number: 10923600
    Abstract: A transistor with stable electrical characteristics. A semiconductor device includes a first insulator over a substrate, a second insulator over the first insulator, an oxide semiconductor in contact with at least part of a top surface of the second insulator, a third insulator in contact with at least part of a top surface of the oxide semiconductor, a first conductor and a second conductor electrically connected to the oxide semiconductor, a fourth insulator over the third insulator, a third conductor which is over the fourth insulator and at least part of which is between the first conductor and the second conductor, and a fifth insulator over the third conductor. The first insulator contains a halogen element.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: February 16, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Mitsuhiro Ichijo, Toshiya Endo, Akihisa Shimomura, Yuji Egi, Sachiaki Tezuka, Shunpei Yamazaki
  • Patent number: 10741679
    Abstract: Provided is a semiconductor device having favorable reliability.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: August 11, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kazutaka Kuriki, Yuji Egi, Hiromi Sawai, Yusuke Nonaka, Noritaka Ishihara, Daisuke Matsubayashi
  • Publication number: 20200135445
    Abstract: A semiconductor device having favorable electrical characteristics is provided. A first insulator is formed over an oxide, a second insulator is formed over the first insulator, a conductor is formed over the second insulator, and a third insulator that is in contact with a top surface of the oxide, a side surface of the first insulator, a side surface of the second insulator, and a side surface of the conductor is formed. The first insulator and the second insulator are successively formed in a reduced-pressure atmosphere.
    Type: Application
    Filed: April 16, 2018
    Publication date: April 30, 2020
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Sachiaki TEZUKA, Hiroki KOMAGATA, Yuji EGI, Naoki OKUNO
  • Publication number: 20190139783
    Abstract: A semiconductor device having high reliability is provided.
    Type: Application
    Filed: April 11, 2017
    Publication date: May 9, 2019
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Kazutaka KURIKI, Yuji EGI, Noritaka ISHIHARA, Yusuke NONAKA, Yasumasa YAMANE, Ryo TOKUMARU, Daisuke MATSUBAYASHI
  • Patent number: 10224433
    Abstract: In a semiconductor device including a transistor in which an oxide semiconductor layer, a gate insulating layer, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor layer and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive layer and an interlayer insulating layer are stacked to cover the oxide semiconductor layer, the sidewall insulating layers, and the gate electrode layer. Then, parts of the interlayer insulating layer and the conductive layer over the gate electrode layer are removed by a chemical mechanical polishing method, so that a source electrode layer and a drain electrode layer are formed. Before formation of the gate insulating layer, cleaning treatment is performed on the oxide semiconductor layer.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: March 5, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuji Egi, Hideomi Suzawa, Shinya Sasagawa
  • Publication number: 20180350997
    Abstract: A transistor with stable electrical characteristics. A semiconductor device includes a first insulator over a substrate, a second insulator over the first insulator, an oxide semiconductor in contact with at least part of a top surface of the second insulator, a third insulator in contact with at least part of a top surface of the oxide semiconductor, a first conductor and a second conductor electrically connected to the oxide semiconductor, a fourth insulator over the third insulator, a third conductor which is over the fourth insulator and at least part of which is between the first conductor and the second conductor, and a fifth insulator over the third conductor. The first insulator contains a halogen element.
    Type: Application
    Filed: July 25, 2018
    Publication date: December 6, 2018
    Inventors: Tetsuhiro TANAKA, Mitsuhiro ICHIJO, Toshiya ENDO, Akihisa SHIMOMURA, Yuji EGI, Sachiaki TEZUKA, Shunpei YAMAZAKI
  • Patent number: 10056497
    Abstract: A transistor with stable electrical characteristics. A semiconductor device includes a first insulator over a substrate, a second insulator over the first insulator, an oxide semiconductor in contact with at least part of a top surface of the second insulator, a third insulator in contact with at least part of a top surface of the oxide semiconductor, a first conductor and a second conductor electrically connected to the oxide semiconductor, a fourth insulator over the third insulator, a third conductor which is over the fourth insulator and at least part of which is between the first conductor and the second conductor, and a fifth insulator over the third conductor. The first insulator contains a halogen element.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: August 21, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Mitsuhiro Ichijo, Toshiya Endo, Akihisa Shimomura, Yuji Egi, Sachiaki Tezuka, Shunpei Yamazaki
  • Publication number: 20180233588
    Abstract: Provided is a semiconductor device having favorable reliability.
    Type: Application
    Filed: April 9, 2018
    Publication date: August 16, 2018
    Inventors: Shunpei Yamazaki, Kazutaka Kuriki, Yuji Egi, Hiromi Sawai, Yusuke Nonaka, Noritaka Ishihara, Daisuke Matsubayashi
  • Patent number: 9947777
    Abstract: Provided is a semiconductor device having favorable reliability.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: April 17, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kazutaka Kuriki, Yuji Egi, Hiromi Sawai, Yusuke Nonaka, Noritaka Ishihara, Daisuke Matsubayashi
  • Patent number: 9806201
    Abstract: A method for forming an oxide that can be used as a semiconductor of a transistor or the like is provided. In particular, a method for forming an oxide with fewer defects such as grain boundaries is provided. One embodiment of the present invention is a semiconductor device including an oxide semiconductor, an insulator, and a conductor. The oxide semiconductor includes a region overlapping with the conductor with the insulator therebetween. The oxide semiconductor includes a crystal grain with an equivalent circle diameter of 1 nm or more and a crystal grain with an equivalent circle diameter less than 1 nm.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: October 31, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshinori Yamada, Yusuke Nonaka, Masashi Oota, Yoichi Kurosawa, Noritaka Ishihara, Takashi Hamada, Mitsuhiro Ichijo, Yuji Egi
  • Publication number: 20170309732
    Abstract: Provided is a semiconductor device having favorable reliability.
    Type: Application
    Filed: April 20, 2017
    Publication date: October 26, 2017
    Inventors: Shunpei YAMAZAKI, Kazutaka KURIKI, Yuji EGI, Hiromi SAWAI, Yusuke NONAKA, Noritaka ISHIHARA, Daisuke MATSUBAYASHI
  • Publication number: 20170200828
    Abstract: In a semiconductor device including a transistor in which an oxide semiconductor layer, a gate insulating layer, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor layer and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive layer and an interlayer insulating layer are stacked to cover the oxide semiconductor layer, the sidewall insulating layers, and the gate electrode layer. Then, parts of the interlayer insulating layer and the conductive layer over the gate electrode layer are removed by a chemical mechanical polishing method, so that a source electrode layer and a drain electrode layer are formed. Before formation of the gate insulating layer, cleaning treatment is performed on the oxide semiconductor layer.
    Type: Application
    Filed: March 23, 2017
    Publication date: July 13, 2017
    Inventors: Yuji EGI, Hideomi SUZAWA, Shinya SASAGAWA
  • Patent number: 9608123
    Abstract: In a semiconductor device including a transistor in which an oxide semiconductor layer, a gate insulating layer, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor layer and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive layer and an interlayer insulating layer are stacked to cover the oxide semiconductor layer, the sidewall insulating layers, and the gate electrode layer. Then, parts of the interlayer insulating layer and the conductive layer over the gate electrode layer are removed by a chemical mechanical polishing method, so that a source electrode layer and a drain electrode layer are formed. Before formation of the gate insulating layer, cleaning treatment is performed on the oxide semiconductor layer.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: March 28, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuji Egi, Hideomi Suzawa, Shinya Sasagawa
  • Publication number: 20160308060
    Abstract: A transistor with stable electrical characteristics. A semiconductor device includes a first insulator over a substrate, a second insulator over the first insulator, an oxide semiconductor in contact with at least part of a top surface of the second insulator, a third insulator in contact with at least part of a top surface of the oxide semiconductor, a first conductor and a second conductor electrically connected to the oxide semiconductor, a fourth insulator over the third insulator, a third conductor which is over the fourth insulator and at least part of which is between the first conductor and the second conductor, and a fifth insulator over the third conductor. The first insulator contains a halogen element.
    Type: Application
    Filed: April 7, 2016
    Publication date: October 20, 2016
    Inventors: Tetsuhiro TANAKA, Mitsuhiro ICHIJO, Toshiya ENDO, Akihisa SHIMOMURA, Yuji EGI, Sachiaki TEZUKA, Shunpei YAMAZAKI
  • Patent number: 9310641
    Abstract: A display device with a higher contrast ratio is provided. The display device is provided with stacked polarizing plates arranged displaced from a parallel nicol state. Moreover, in the display device, at least one of a pair of stacked polarizing plates is displaced from a parallel state. The pair of stacked polarizing plates is arranged in a cross nicol state. A retardation plate may be provided between the polarizing plate and the substrate. As a result, the contrast ratio can be increased.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: April 12, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuji Egi, Tetsuji Ishitani, Takeshi Nishi
  • Patent number: 9164313
    Abstract: To provide a display device having a high contrast ratio by a simple and easy method and to manufacture a high-performance display device at low cost, in a display device having a display element between a pair of light-transmitting substrates, layers each including a polarizer having different wavelength distribution of extinction coefficient from each other with respect to the absorption axes are stacked and provided on an outer side of the light-transmitting substrates. Further, a retardation plate may be provided between the stacked polarizers.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: October 20, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuji Egi, Tetsuji Ishitani, Takeshi Nishi
  • Publication number: 20150255534
    Abstract: A method for forming an oxide that can be used as a semiconductor of a transistor or the like is provided. In particular, a method for forming an oxide with fewer defects such as grain boundaries is provided. One embodiment of the present invention is a semiconductor device including an oxide semiconductor, an insulator, and a conductor. The oxide semiconductor includes a region overlapping with the conductor with the insulator therebetween. The oxide semiconductor includes a crystal grain with an equivalent circle diameter of 1 nm or more and a crystal grain with an equivalent circle diameter less than 1 nm.
    Type: Application
    Filed: March 3, 2015
    Publication date: September 10, 2015
    Inventors: Shunpei YAMAZAKI, Yoshinori YAMADA, Yusuke NONAKA, Masashi OOTA, Yoichi KUROSAWA, Noritaka ISHIHARA, Takashi HAMADA, Mitsuhiro ICHIJO, Yuji EGI