Patents by Inventor Yuji Judai

Yuji Judai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6498094
    Abstract: An underlying conductive film made of iridium and having a thickness of about 0.1 &mgr;m is formed in a contact hole formed in an insulating film covering a transistor formed in a substrate, except in the top portion of the contact hole. The underlying conductive film covers the sidewall portions of the contact hole and the top surface of the drain region but does not completely fill in the contact hole. A plug made of platinum is filled in the contact hole up to the top portion thereof. Over the contact hole of the insulating film, there is formed a capacitor composed of a lower electrode made of platinum, a capacitor insulating film made of SrBi2Ta2O9, and an upper electrode made of platinum in contact relation with the respective upper ends of the underlying conductive film and the plug.
    Type: Grant
    Filed: July 1, 1999
    Date of Patent: December 24, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Keisaku Nakao, Yoichi Sasai, Yuji Judai, Atsushi Noma
  • Publication number: 20020155663
    Abstract: A semiconductor device includes: a silicon substrate; a MOS semiconductor device provided on the silicon substrate, the MOS semiconductor device including a silicide region on an outermost surface thereof; a first insulating film covering the MOS semiconductor device; a capacitor element provided on the first insulating film, the capacitor element comprising a lower electrode, an upper electrode, and a capacitor film interposed between the lower electrode and the upper electrode, and the capacitor film comprising a ferroelectric material; a second insulating film covering the first insulating film and the capacitor element; a contact hole provided in the first insulating film and the second insulating film over the MOS semiconductor device and the capacitor element; and an interconnection layer provided on the second insulating film for electrically connecting the MOS semiconductor device and the capacitor element to each other, wherein a bottom portion of the interconnection layer comprises a conductive mate
    Type: Application
    Filed: June 20, 2002
    Publication date: October 24, 2002
    Inventors: Yoshihisa Nagano, Yasuhiro Uemoto, Yuji Judai, Masamichi Azuma, Eiji Fujii
  • Publication number: 20020149082
    Abstract: A semiconductor device includes: a capacitor provided on a supporting substrate having an integrated circuit thereon and including a lower electrode, a dielectric film, and an upper electrode; a first interlayer insulating film provided so as to cover the capacitor; a first interconnect selectively provided on the first interlayer insulating film and electrically connected to the integrated circuit and the capacitor through a first contact hole formed in the first interlayer insulating film; a second interlayer insulating film formed of ozone TEOS and provided so as to cover the first interconnect; a second interconnect selectively provided on the second interlayer insulating film and electrically connected to the first interconnect through a second contact hole formed in the second interlayer insulating film; and a passivation layer provided so as to cover the second interconnect.
    Type: Application
    Filed: June 12, 2002
    Publication date: October 17, 2002
    Inventors: Yoshihisa Nagano, Toshie Kutsunai, Yuji Judai, Yasuhiro Uemoto, Eiji Fuji
  • Publication number: 20020115226
    Abstract: The ferroelectric memory device has a plurality of capacitor elements each formed on a semiconductor substrate and composed of a lower electrode, a capacitor insulating film made of a ferroelectric material formed on the lower electrode, and an upper electrode formed on the capacitor insulating film. Each of the lower electrodes is buried in a burying insulating film to have an upper surface planarized relative to the upper surface of the burying insulating film and has a plane configuration such that the distance from an arbitrary position on the upper surface of the lower electrode to the nearest end portion thereof is 0.6 &mgr;m or less.
    Type: Application
    Filed: November 13, 2001
    Publication date: August 22, 2002
    Inventors: Takumi Mikawa, Toshie Kutsunai, Yuji Judai
  • Publication number: 20020056861
    Abstract: A semiconductor device includes: a capacitor provided on a supporting substrate having an integrated circuit thereon and including a lower electrode, a dielectric film, and an upper electrode; a first interlayer insulating film provided so as to cover the capacitor; a first interconnect selectively provided on the first interlayer insulating film and electrically connected to the integrated circuit and the capacitor through a first contact hole formed in the first interlayer insulating film; a second interlayer insulating film formed of ozone TEOS and provided so as to cover the first interconnect; a second interconnect selectively provided on the second interlayer insulating film and electrically connected to the first interconnect through a second contact hole formed in the second interlayer insulating film; and a passivation layer provided so as to cover the second interconnect.
    Type: Application
    Filed: June 24, 1998
    Publication date: May 16, 2002
    Inventors: YOSHIHISA NAGANO, TOSHIE KUTSUNAI, YUJI JUDAI, YASUHIRO UEMOTO, EIJI FUJII
  • Publication number: 20020055223
    Abstract: An impurity diffusion layer serving as the source or the drain of a transistor is formed in a semiconductor substrate, and a protection insulating film is formed so as to cover the transistor. A capacitor lower electrode, a capacitor dielectric film of an oxide dielectric film and a capacitor upper electrode are successively formed on the protection insulating film. A plug for electrically connecting the impurity diffusion layer of the transistor to the capacitor lower electrode is buried in the protection insulating film. An oxygen barrier layer is formed between the plug and the capacitor lower electrode. The oxygen barrier layer is made from a composite nitride that is a mixture or an alloy of a first nitride having a conducting property and a second nitride having an insulating property.
    Type: Application
    Filed: August 6, 2001
    Publication date: May 9, 2002
    Inventors: Toshie Kutsunai, Shinichiro Hayashi, Takumi Mikawa, Yuji Judai
  • Publication number: 20020047111
    Abstract: A semiconductor device has
    Type: Application
    Filed: November 21, 2001
    Publication date: April 25, 2002
    Inventor: Yuji Judai
  • Publication number: 20020030243
    Abstract: A lower electrode is formed on a substrate, a capacitive insulating film is formed out of a ferroelectric film on the lower electrode, and an upper electrode is formed on the capacitive insulating film. A contact layer is formed on the upper electrode. The contact layer is either a single-layer film made of a metal oxide or a metal nitride or a multilayer structure made up of metal oxide and metal nitride films. An insulating film is formed to cover the lower electrode, capacitive insulating film, upper electrode and contact layer. A contact hole is opened through the insulating film and the contact layer to reach the upper electrode. A metal interconnect, which is filled in the contact hole and connected to the upper electrode, is formed on a part of the insulating film.
    Type: Application
    Filed: December 12, 2000
    Publication date: March 14, 2002
    Inventors: Takumi Mikawa, Yuji Judai
  • Publication number: 20020000589
    Abstract: A semiconductor device includes: a silicon substrate; a MOS semiconductor device provided on the silicon substrate, the MOS semiconductor device including a silicide region on an outermost surface thereof; a first insulating film covering the MOS semiconductor device; a capacitor element provided on the first insulating film, the capacitor element comprising a lower electrode, an upper electrode, and a capacitor film interposed between the lower electrode and the upper electrode, and the capacitor film comprising a ferroelectric material; a second insulating film covering the first insulating film and the capacitor element; a contact hole provided in the first insulating film and the second insulating film over the MOS semiconductor device and the capacitor element; and an interconnection layer provided on the second insulating film for electrically connecting the MOS semiconductor device and the capacitor element to each other, wherein a bottom portion of the interconnection layer comprises a conductive mate
    Type: Application
    Filed: November 12, 1998
    Publication date: January 3, 2002
    Inventors: YOSHIHISA NAGANO, YASUHIRO UEMOTO, YUJI JUDAI, MASAMICHI AZUMA, EIJI FUJII
  • Publication number: 20020000588
    Abstract: A semiconductor device has
    Type: Application
    Filed: October 22, 1998
    Publication date: January 3, 2002
    Inventor: YUJI JUDAI
  • Publication number: 20010028074
    Abstract: A capacitor including a capacitor lower electrode, a capacitor dielectric film of a highly dielectric film or a ferroelectric film and a capacitor upper electrode is formed on a semiconductor substrate. A protection film is formed on the semiconductor substrate so as to cover the capacitor. A first TEOS film having a relatively large water content is formed on the protection film through first TEOS-O3 CVD where an ozone concentration is relatively low. A second TEOS-O3 film having a relatively small water content is formed on the first TEOS-O3 film through second TEOS-O3 CVD where the ozone concentration is relatively high.
    Type: Application
    Filed: February 9, 2001
    Publication date: October 11, 2001
    Inventors: Toshie Kutsunai, Shinichiro Hayashi, Yuji Judai, Yoshihisa Nagano
  • Publication number: 20010023129
    Abstract: An underlying conductive film made of iridium and having a thickness of about 0.1 &mgr;m is formed in a contact hole formed in an insulating film covering a transistor formed in a substrate, except in the top portion of the contact hole. The underlying conductive film covers the sidewall portions of the contact hole and the top surface of the drain region but does not completely fill in the contact hole. A plug made of platinum is filled in the contact hole up to the top portion thereof. Over the contact hole of the insulating film, there is formed a capacitor composed of a lower electrode made of platinum, a capacitor insulating film made of SrBi2Ta2O9, and an upper electrode made of platinum in contact relation with the respective upper ends of the underlying conductive film and the plug.
    Type: Application
    Filed: July 1, 1999
    Publication date: September 20, 2001
    Inventors: KEISAKU NAKAO, YOICHI SASAI, YUJI JUDAI, ATSUSHI NOMA
  • Patent number: 6174822
    Abstract: A semiconductor device includes: a capacitor provided on a supporting substrate having an integrated circuit thereon and including a lower electrode, a dielectric film, and an upper electrode; a first interlayer insulating film provided so as to cover the capacitor; a first interconnect selectively provided on the first interlayer insulating film and electrically connected to the integrated circuit and the capacitor through a first contact hole formed in the first interlayer insulating film; a second interlayer insulating film formed of ozone TEOS and provided so as to cover the first interconnect; a second interconnect selectively provided on the second interlayer insulating film and electrically connected to the first interconnect through a second contact hole formed in the second interlayer insulating film; and a passivation layer provided so as to cover the second interconnect.
    Type: Grant
    Filed: October 20, 1998
    Date of Patent: January 16, 2001
    Assignee: Matsushita Electronics Corporation
    Inventors: Yoshihisa Nagano, Toshie Kutsunai, Yuji Judai, Yasuhiro Uemoto, Eiji Fujii
  • Patent number: 6166424
    Abstract: On a substrate, there are provided a lower electrode, a capacitance insulating film, a passivation insulating film, and a first partial film of an upper electrode to be filled in a second aperture (capacitance determining aperture) formed in the passivation insulating film. The lower electrode, the capacitance insulating film, and the first partial film constitute a capacitance element. The upper electrode has the first partial film which is in contact with the capacitance insulating film and a second partial film which is not in contact with the capacitance insulating film. Since a second electrode wire consisting of a lower-layer film composed of titanium and an upper-layer film composed of an aluminum alloy film is in contact with the second partial film distinct from the first partial film of the upper electrode, titanium or the like encroaching from the second electrode wire can be prevented from diffusing into the capacitance insulating film.
    Type: Grant
    Filed: July 2, 1998
    Date of Patent: December 26, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Takumi Mikawa, Yuji Judai, Yoshihisa Nagano