Abstract: An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part, an electrically connecting member, and a sealing member. A method of producing an electronic part embedded substrate is also disclosed. The method includes mounting an electronic part onto a first substrate, laminating a second substrate on the first substrate through an electrically connecting member; and filling a space between the first substrate and the second substrate with a sealing member to seal the electronic part.

Abstract: A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip.

Abstract: A semiconductor device includes a first insulating layer; a wiring layer formed on a first surface of the first insulating layer and including a first electrode pad; a semiconductor chip; a second insulating layer including a semiconductor chip accommodating portion; a third insulating layer on the second insulating layer; and a passive element including an electrode and formed of an embedded portion and a protruding portion on a second surface of the first insulating layer, wherein an end surface of the embedded portion is coated by the insulating layer, the electrode of the passive element is electrically connected to the wiring layer through a via wiring formed in the insulating layers, the first electrode pad is electrically connected to another semiconductor device through a joining portion, and a protruding amount of the protruding portion is less than a gap between the second surface and the another semiconductor device.

Abstract: A semiconductor device includes a first insulating layer; a wiring layer formed on a first surface of the first insulating layer and including a first electrode pad; a semiconductor chip; a second insulating layer including a semiconductor chip accommodating portion; a third insulating layer on the second insulating layer; and a passive element including an electrode and formed of an embedded portion and a protruding portion on a second surface of the first insulating layer, wherein an end surface of the embedded portion is coated by the insulating layer, the electrode of the passive element is electrically connected to the wiring layer through a via wiring formed in the insulating layers, the first electrode pad is electrically connected to another semiconductor device through a joining portion, and a protruding amount of the protruding portion is less than a gap between the second surface and the another semiconductor device.

Abstract: At least one electronic component having a plurality of terminals on one of surfaces is temporarily fixed to a surface of a first support with a first adhesive layer in such a manner that the terminal side of the electronic component faces the first support. A second support having a second adhesive layer is fixed to the electronic component in order to interpose the electronic component between the first support and the second support. The first support and the first adhesive layer are peeled. The electronic component on the second support is sealed with a sealing resin in such a manner that at least a part of the terminals of the electronic component is exposed. An insulating resin layer and a wiring layer to be electrically connected to the terminal of the electronic component are stacked on the electronic component and the sealing resin.

Abstract: A semiconductor device includes a semiconductor element having a first surface on which an electrode terminal is formed, and a second surface located opposite to the first surface. The semiconductor device further includes a first insulating layer in which the semiconductor element is buried, and second insulating layers and wiring layers formed in such a manner that at least one insulating layer and at least one wiring layer are formed on each of both surfaces of the first insulating layer. The electrode terminal of the semiconductor element is connected to a first wiring layer located on the first surface side through a first via formed in the first insulating layer, and the first wiring layer is connected to a second wiring layer located on the second surface side through a second via formed in the first insulating layer.

Abstract: A wiring substrate includes: a substrate layer made of glass or silicon and including: a first surface formed with a first hole; and a second surface formed with a second hole and being opposite to the first surface, wherein the first hole is communicated with the second hole; a connection pad formed in the second hole; a first wiring layer formed in the first hole and electrically connected to the connection pad; a first insulation layer formed on the first surface of the substrate layer to cover the first wiring layer; and a second wiring layer formed on the first insulation layer and electrically connected to the first wiring layer. A diameter of the first hole is gradually decreased from the first surface toward the second surface, and a diameter of the second hole is gradually decreased from the second surface toward the first surface.

Abstract: A method of producing a resin-sealed package is provided with: providing an electronic component which has a plurality of terminals on one face, a first support member and a second support member; temporarily fixing said electronic component to a surface of said first support member by a first adhesive agent layer, to face said terminals with said first support member; fixing said second support member having a second adhesive agent layer to said electronic component while interposing said electronic component between said first support member and said second support member to face said second adhesive agent layer with a back face side of said electronic component; resin sealing said electronic component between said first support member and said second support member; peeling said first support member and said first adhesive agent layer from said electronic component and a sealing resin; and stacking an insulating resin layer and a wiring layer which is electrically connected to said terminals of said electr

Abstract: A chip is bonded onto a flat face of a first support through a first bonding layer with a terminal surface of the chip turned toward the flat face of the first support. A second support is bonded onto the chip through a second bonding layer. The first support is peeled from the chip to expose the terminal surface of the chip. An insulating layer from which the terminal surface of the chip is exposed is formed on the second support.

Abstract: A wiring board with lead pins includes: connection pads formed on a wiring board, and lead pins bonded through a conductive material to the connection pads, wherein each of the lead pins has a head portion that is formed in one end of a shaft portion to be larger in diameter than the shaft portion, the head portions are bonded to the connection pads by the conductive material, a face of the wiring board on which the connection pads are formed is resin-sealed by a first resin to be thicker than the head portions, except portions to which the head portions are bonded, and sides of faces of the head portions to which the shaft portions are connected are sealed to be in close contact with the first resin by a second resin.

Abstract: A plurality of semiconductor devices having different thicknesses from each other and having respective electrode terminals are fixed on a surface of the support plate through a resin layer in such a manner that terminal surfaces of the electrode terminals are on the level with each other. An insulating layer covers terminal forming surfaces of the semiconductor devices. At least one tapered bump having a tip surface formed in a smaller area than an area of the terminal surface of the electrode terminal of the semiconductor device is formed on one of the terminal surfaces of the electrode terminals and penetrates the insulating layer in such a manner that the tip surface of the tapered bump is exposed to a surface of the insulating layer. A wiring pattern is formed on the surface of the insulating layer and connected to the tip surface of the tapered bump.

Abstract: A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip.

Abstract: A semiconductor device includes a semiconductor element having a first surface on which an electrode terminal is formed, and a second surface located opposite to the first surface. The semiconductor device further includes a first insulating layer in which the semiconductor element is buried, and second insulating layers and wiring layers formed in such a manner that at least one insulating layer and at least one wiring layer are formed on each of both surfaces of the first insulating layer. The electrode terminal of the semiconductor element is connected to a first wiring layer located on the first surface side through a first via formed in the first insulating layer, and the first wiring layer is connected to a second wiring layer located on the second surface side through a second via formed in the first insulating layer.

Abstract: A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip.

Abstract: A first sealing resin seals a side surface of an electronic component and a side surface of a conductive member. A second sealing resin is provided on the first sealing resin, and seals an electrode pad and an electrode pad forming surface of the electronic component and a part of the conductive member. A multilayer wiring structure includes a plurality of stacked insulating layers and a wiring pattern and is provided on a surface of the second sealing resin from which a connecting surface of the electrode pad and a first connecting surface of the conductive member are exposed. The wiring pattern is connected to the connecting surface of the electrode pad and the first connecting surface of the conductive member.

Abstract: A method of producing a resin-sealed package is provided with: providing an electronic component which has a plurality of terminals on one face, a first support member and a second support member; temporarily fixing said electronic component to a surface of said first support member by a first adhesive agent layer, to face said terminals with said first support member; fixing said second support member having a second adhesive agent layer to said electronic component while interposing said electronic component between said first support member and said second support member to face said second adhesive agent layer with a back face side of said electronic component; resin sealing said electronic component between said first support member and said second support member; peeling said first support member and said first adhesive agent layer from said electronic component and a sealing resin; and stacking an insulating resin layer and a wiring layer which is electrically connected to said terminals of said electr

Abstract: At least one electronic component having a plurality of terminals on one of surfaces is temporarily fixed to a surface of a first support with a first adhesive layer in such a manner that the terminal side of the electronic component faces the first support. A second support having a second adhesive layer is fixed to the electronic component in order to interpose the electronic component between the first support and the second support. The first support and the first adhesive layer are peeled. The electronic component on the second support is sealed with a sealing resin in such a manner that at least a part of the terminals of the electronic component is exposed. An insulating resin layer and a wiring layer to be electrically connected to the terminal of the electronic component are stacked on the electronic component and the sealing resin.

Abstract: A wiring board with lead pins includes: connection pads formed on a wiring board, and lead pins bonded through a conductive material to the connection pads, wherein each of the lead pins has a head portion that is formed in one end of a shaft portion to be larger in diameter than the shaft portion, the head portions are bonded to the connection pads by the conductive material, a face of the wiring board on which the connection pads are formed is resin-sealed by a first resin to be thicker than the head portions, except portions to which the head portions are bonded, and sides of faces of the head portions to which the shaft portions are connected are sealed to be in close contact with the first resin by a second resin.

Abstract: A plurality of semiconductor devices having different thicknesses from each other and having respective electrode terminals are fixed on a surface of the support plate through a resin layer in such a manner that terminal surfaces of the electrode terminals are on the level with each other. An insulating layer covers terminal forming surfaces of the semiconductor devices. At least one tapered bump having a tip surface formed in a smaller area than an area of the terminal surface of the electrode terminal of the semiconductor device is formed on one of the terminal surfaces of the electrode terminals and penetrates the insulating layer in such a manner that the tip surface of the tapered bump is exposed to a surface of the insulating layer. A wiring pattern is formed on the surface of the insulating layer and connected to the tip surface of the tapered bump.

Abstract: A chip is bonded onto a flat face of a first support through a first bonding layer with a terminal surface of the chip turned toward the flat face of the first support. A second support is bonded onto the chip through a second bonding layer. The first support is peeled from the chip to expose the terminal surface of the chip. An insulating layer from which the terminal surface of the chip is exposed is formed on the second support.