Patents by Inventor Yuji Masui

Yuji Masui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150010032
    Abstract: A light-emitting element includes a mesa structure in which a first compound semiconductor layer of a first conductivity type, an active layer, and a second compound semiconductor layer of a second conductivity type are disposed in that order, wherein at least one of the first compound semiconductor layer and the second compound semiconductor layer has a current constriction region surrounded by an insulation region extending inward from a sidewall portion of the mesa structure; a wall structure disposed so as to surround the mesa structure; at least one bridge structure connecting the mesa structure and the wall structure, the wall structure and the bridge structure each having the same layer structure as the portion of the mesa structure in which the insulation region is provided; a first electrode; and a second electrode disposed on a top face of the wall structure.
    Type: Application
    Filed: May 8, 2014
    Publication date: January 8, 2015
    Applicant: SONY CORPORATION
    Inventors: Tomoyuki Oki, Yuji Masui, Yoshinori Yamauchi, Rintaro Koda, Takahiro Arakida
  • Patent number: 8761221
    Abstract: A light-emitting element includes a mesa structure in which a first compound semiconductor layer of a first conductivity type, an active layer, and a second compound semiconductor layer of a second conductivity type are disposed in that order, wherein at least one of the first compound semiconductor layer and the second compound semiconductor layer has a current constriction region surrounded by an insulation region extending inward from a sidewall portion of the mesa structure; a wall structure disposed so as to surround the mesa structure; at least one bridge structure connecting the mesa structure and the wall structure, the wall structure and the bridge structure each having the same layer structure as the portion of the mesa structure in which the insulation region is provided; a first electrode; and a second electrode disposed on a top face of the wall structure.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: June 24, 2014
    Assignee: Sony Corporation
    Inventors: Tomoyuki Oki, Yuji Masui, Yoshinori Yamauchi, Rintaro Koda, Takahiro Arakida
  • Patent number: 8514905
    Abstract: A laser diode with which separation of a current narrowing layer is able to be prevented is provided. The laser diode includes a mesa that has a first multilayer film reflector, an active layer, and a second multilayer film reflector in this order, and has a current narrowing layer for narrowing a current injected into the active layer and a buffer layer adjacent to the current narrowing layer. The current narrowing layer is formed by oxidizing a first oxidized layer containing Al. The buffer layer is formed by oxidizing a second oxidized layer whose material and a thickness are selected so that an oxidation rate is higher than that of the first multilayer film reflector and the second multilayer film reflector and is lower than that of the first oxidized layer. A thickness of the buffer layer is 10 nm or more.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: August 20, 2013
    Assignee: Sony Corporation
    Inventors: Yuji Masui, Rintaro Koda, Tomoyuki Oki, Takahiro Arakida, Naoki Jogan, Yoshinori Yamauchi
  • Patent number: 8497141
    Abstract: A method of manufacturing a semiconductor device capable of largely increasing the yield and a semiconductor device manufactured by using the method is provided. After a semiconductor layer is formed on a substrate, as one group, a plurality of functional portions with at least one parameter value different from each other is formed in the semiconductor layer for every unit chip area. Then, a subject that is changed depending on the parameter value is measured and evaluated and after that, the substrate is divided for every chip area so that a functional portion corresponding with a given criterion as a result of the evaluation is not broken. Thereby, at least one functional portion corresponding with a given criterion can be formed by every chip area by appropriately adjusting each parameter value.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: July 30, 2013
    Assignee: Sony Corporation
    Inventors: Yuji Masui, Takahiro Arakida, Yoshinori Yamauchi, Kayoko Kikuchi, Rintaro Koda, Norihiko Yamaguchi
  • Patent number: 8450752
    Abstract: The present invention provides a semiconductor device realizing reduced occurrence of a defect such as a crack at the time of adhering elements to each other. The semiconductor device includes a first element and a second element adhered to each other. At least one of the first and second elements has a pressure relaxation layer on the side facing the other of the first and second elements, and the pressure relaxation layer includes a semiconductor part having a projection/recess part including a projection projected toward the other element, and a resin part filled in a recess in the projection/recess part.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: May 28, 2013
    Assignee: Sony Corporation
    Inventors: Rintaro Koda, Takahiro Arakida, Yuji Masui, Tomoyuki Oki
  • Patent number: 8385381
    Abstract: In a VCSEL, a first multilayer film reflector, an active layer having a light emitting central region, a second multilayer film reflector, and a transverse mode adjustment layer are layered in this order. The first multilayer film reflector has a quadrangle current injection region with an intersection of diagonal lines corresponding to the light emitting central region. The second multilayer film reflector has a light emitting window provided in a region corresponding to one diagonal line of the current injection region and a pair of grooves provided with the light emitting window in between. The transverse mode adjustment layer is provided correspondingly to the light emitting window, and reflectance of a peripheral region thereof is lower than that of a central region thereof.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: February 26, 2013
    Assignee: Sony Corporation
    Inventors: Osamu Maeda, Masaki Shiozaki, Norihiko Yamaguchi, Yoshinori Yamauchi, Yuji Masui
  • Patent number: 8372670
    Abstract: A method for making a light-emitting element assembly including a support substrate having a first surface, a second surface facing the first surface, a recessed portion, and a conductive material layer formed over the first surface and the inner surface of the recessed portion, and a light-emitting element. The light-emitting element has a laminated structure including a first compound semiconductor layer, a light-emitting portion, and a second compound semiconductor layer, at least the second compound semiconductor layer and the light-emitting portion constituting a mesa structure. The light-emitting element further includes an insulating layer formed, a second electrode, and a first electrode. The mesa structure is placed in the recessed portion so that the conductive material layer and the second electrode are in at least partial contact with each other, and light emitted from the light-emitting portion is emitted from the second surface side of the first compound semiconductor layer.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: February 12, 2013
    Assignee: Sony Corporation
    Inventors: Rintaro Koda, Takahiro Arakida, Satoshi Taniguchi, Yuji Masui, Nobuhiro Suzuki, Tomoyuki Oki, Chiyomi Uchiyama, Kayoko Kikuchi
  • Patent number: 8290009
    Abstract: A vertical cavity surface emitting laser includes a layer-stack structure including, on a substrate, a transverse-mode adjustment layer, a first multilayer reflecting mirror, an active layer having a light emission region, and a second multilayer reflecting mirror in order from the substrate side, and including a current confinement layer in which a current injection region is formed in a region corresponding to the light emission region in the first multilayer reflecting mirror, between the first multilayer reflecting mirror and the active layer, between the active layer and the second multilayer reflecting mirror, or in the second multilayer reflecting mirror. In the transverse-mode adjustment layer, reflectance at an oscillation wavelength in the region opposite to a center of the light emission region is higher than that at an oscillation wavelength in the region opposite to an outer edge of the light emission region.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: October 16, 2012
    Assignee: Sony Corporation
    Inventors: Yuji Masui, Takahiro Arakida, Rintaro Koda, Osamu Maeda, Tomoyuki Oki, Naoki Jogan
  • Publication number: 20120175670
    Abstract: A method for manufacturing a light emitting element including the steps of (A) sequentially forming on a substrate a first compound semiconductor layer having a first conduction type, an active layer, and a second compound semiconductor layer having a second conduction type; (B) forming a plurality of point-like hole portions in a thickness direction in at least a region of the second compound semiconductor layer located outside a region to be provided with a current confinement region; and (C) forming an insulating region by subjecting a part of the second compound semiconductor layer to an insulation treatment from side walls of the hole portions so as to produce the current confinement region surrounded by the insulating region in the second compound semiconductor layer.
    Type: Application
    Filed: March 20, 2012
    Publication date: July 12, 2012
    Applicant: SONY CORPORATION
    Inventors: Yuji Masui, Takahiro Arakida, Rintaro Koda, Tomoyuki Oki
  • Patent number: 8218596
    Abstract: A Vertical Cavity Surface Emitting Laser capable of decreasing the lowering of the yield due to displacement and separation of a pedestal without enormous increase of the threshold value and more difficult manufacturing process is provided. A base of a mesa spreads over the top face of a lower DBR layer. The base is a non-flat face in which end faces of a plurality of layers are exposed. The non-flat face is generated due to etching unevenness in forming the mesa, and is in a state of a step in which end faces of a low-refractive index layer and a high-refractive index layer included in the lower DBR layer are alternatively exposed. At least one of the layers exposed in the non-flat face in the plurality of low-refractive index layers included in the lower DBR layer is an oxidation inhibition layer.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: July 10, 2012
    Assignee: Sony Corporation
    Inventors: Tomoyuki Oki, Rintaro Koda, Naoki Jogan, Yuji Masui, Takahiro Arakida
  • Patent number: 8218594
    Abstract: The present invention provides a Vertical Cavity Surface Emitting Laser including: a first multilayer film reflector; an active layer having a light emission region; a second multilayer film reflector; and a reflectance adjustment layer in this order on a substrate side. The first multilayer film reflector and the second multilayer film reflector have a laminated structure in which reflectance of oscillation wavelength ?x is almost constant without depending on temperature change. The active layer is made of a material with which a maximum gain is obtained at temperature higher than ambient temperature. The reflectance adjustment layer has a laminated structure in which difference ?R(=Rx?Ry) between reflectance Rx of a region opposed to a central region of the light emission region and reflectance Ry of a region opposed to an outer edge region of the light emission region is increased associated with temperature increase from ambient temperature to high temperature.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: July 10, 2012
    Assignee: Sony Corporation
    Inventors: Osamu Maeda, Yuji Masui, Masaki Shiozaki, Takahiro Arakida, Takayuki Kawasumi
  • Patent number: 8183074
    Abstract: A method for manufacturing a light emitting element includes the steps of (A) forming sequentially a first compound semiconductor layer having a first conduction type, an active layer, and a second compound semiconductor layer having a second conduction type on a substrate, (B) forming a plurality of point-like hole portions in a thickness direction in at least a region of the second compound semiconductor layer located outside a region to be provided with a current confinement region, and (C) forming an insulating region by subjecting a part of the second compound semiconductor layer to an insulation treatment from side walls of the hole portions so as to produce the current confinement region surrounded by the insulating region in the second compound semiconductor layer.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: May 22, 2012
    Assignee: Sony Corporation
    Inventors: Yuji Masui, Takahiro Arakida, Rintaro Koda, Tomoyuki Oki
  • Publication number: 20120034720
    Abstract: A Vertical Cavity Surface Emitting Laser capable of decreasing the lowering of the yield due to displacement and separation of a pedestal without enormous increase of the threshold value and more difficult manufacturing process is provided. A base of a mesa spreads over the top face of a lower DBR layer. The base is a non-flat face in which end faces of a plurality of layers are exposed. The non-flat face is generated due to etching unevenness in forming the mesa, and is in a state of a step in which end faces of a low-refractive index layer and a high-refractive index layer included in the lower DBR layer are alternatively exposed. At least one of the layers exposed in the non-flat face in the plurality of low-refractive index layers included in the lower DBR layer is an oxidation inhibition layer.
    Type: Application
    Filed: October 12, 2011
    Publication date: February 9, 2012
    Applicant: Sony Corporation
    Inventors: Tomoyuki Oki, Rintaro Koda, Naoki Jogan, Yuji Masui, Takahiro Arakida
  • Patent number: 8102890
    Abstract: A semiconductor light emitting device includes a first-conductivity-type first multilayer film reflecting mirror, and a second-conductivity-type second multilayer film reflecting mirror; a cavity layer; and a first conductive section, a second conductive section, and a third conductive section. The cavity layer has a stacked configuration including a first-conductivity-type or undoped first cladding layer, an undoped first active layer, a second-conductivity-type or undoped second cladding layer, a second-conductivity-type first contact layer, a first-conductivity-type second contact layer, a first-conductivity-type or undoped third cladding layer, an undoped second active layer, and a second-conductivity-type or undoped fourth cladding layer.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: January 24, 2012
    Assignee: Sony Corporation
    Inventors: Yuji Masui, Takahiro Arakida, Yoshinori Yamauchi, Rintaro Koda, Tomoyuki Oki, Naoki Jogan
  • Patent number: 8098703
    Abstract: A laser diode allowed to stabilize the polarization direction of laser light in one direction is provided. The laser diode includes a laminate configuration including a lower multilayer reflecting mirror, an active layer and an upper multilayer reflecting mirror in order from a substrate side, in which the laminate configuration includes a columnar mesa section including an upper part of the lower multilayer reflecting mirror, the active layer and the upper multilayer reflecting mirror, and the lower multilayer reflecting mirror includes a plurality of pairs of a low refractive index layer and a high refractive index layer, and a plurality of oxidation layers nonuniformly distributed in a direction rotating around a central axis of the mesa section in a region except for a central region of one or more of the low refractive index layers.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: January 17, 2012
    Assignee: Sony Corporation
    Inventors: Osamu Maeda, Yuji Masui, Masaki Shiozaki, Susumu Sato, Takahiro Arakida
  • Publication number: 20120009704
    Abstract: A vertical cavity surface emitting laser capable of reducing parasitic capacitance while suppressing power consumption, and a method of manufacturing thereof are provided. The vertical cavity surface emitting laser includes a columnar mesa including, on a substrate, a first multilayer reflector, an active layer, and a second multilayer reflector in order from the substrate side, and also including a current narrowing layer. The columnar portion of the mesa including the active layer and the current narrowing layer is formed within a region opposed to the first multilayer reflector and a region opposed to the second multilayer reflector, and a cross section area of the columnar portion is smaller than a cross section area of the second multilayer reflector.
    Type: Application
    Filed: September 19, 2011
    Publication date: January 12, 2012
    Applicant: Sony Corporation
    Inventors: Yuji Masui, Takahiro Arakida, Terukazu Naruse, Rintaro Koda, Naoki Jogan
  • Patent number: 8085827
    Abstract: A Vertical Cavity Surface Emitting Laser capable of decreasing the lowering of the yield due to displacement and separation of a pedestal without enormous increase of the threshold value and more difficult manufacturing process is provided. A base of a mesa spreads over the top face of a lower DBR layer. The base is a non-flat face in which end faces of a plurality of layers are exposed. The non-flat face is generated due to etching unevenness in forming the mesa, and is in a state of a step in which end faces of a low-refractive index layer and a high-refractive index layer included in the lower DBR layer are alternatively exposed. At least one of the layers exposed in the non-flat face in the plurality of low-refractive index layers included in the lower DBR layer is an oxidation inhibition layer.
    Type: Grant
    Filed: March 3, 2009
    Date of Patent: December 27, 2011
    Assignee: Sony Corporation
    Inventors: Tomoyuki Oki, Rintaro Koda, Naoki Jogan, Yuji Masui, Takahiro Arakida
  • Publication number: 20110294236
    Abstract: A method of manufacturing a semiconductor device capable of largely increasing the yield and a semiconductor device manufactured by using the method is provided. After a semiconductor layer is formed on a substrate, as one group, a plurality of functional portions with at least one parameter value different from each other is formed in the semiconductor layer for every unit chip area. Then, a subject that is changed depending on the parameter value is measured and evaluated and after that, the substrate is divided for every chip area so that a functional portion corresponding with a given criterion as a result of the evaluation is not broken. Thereby, at least one functional portion corresponding with a given criterion can be formed by every chip area by appropriately adjusting each parameter value.
    Type: Application
    Filed: August 8, 2011
    Publication date: December 1, 2011
    Applicant: Sony Corporation
    Inventors: Yuji Masui, Takahiro Arakida, Yoshinori Yamauchi, Kayoko Kikuchi, Rintaro Koda, Norihiko Yamaguchi
  • Patent number: 8040934
    Abstract: A vertical cavity surface emitting laser capable of reducing parasitic capacitance while suppressing power consumption, and a method of manufacturing thereof are provided. The vertical cavity surface emitting laser includes a columnar mesa including, on a substrate, a first multilayer reflector, an active layer, and a second multilayer reflector in order from the substrate side, and also including a current narrowing layer. The columnar portion of the mesa including the active layer and the current narrowing layer is formed within a region opposed to the first multilayer reflector and a region opposed to the second multilayer reflector, and a cross section area of the columnar portion is smaller than a cross section area of the second multilayer reflector.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: October 18, 2011
    Assignee: Sony Corporation
    Inventors: Yuji Masui, Takahiro Arakida, Terukazu Naruse, Rintaro Koda, Naoki Jogan
  • Publication number: 20110249696
    Abstract: There is provided a laser diode capable of setting a mesa diameter small without use of a method which loses reliability of a device, and is not easily controlled. The laser diode includes: a columnar mesa including a first multilayer film reflecting mirror, an active layer, and a second multilayer film reflecting mirror in this order, including an oxide confined layer having an unoxidized region in middle of a plane, and having a cross-sectional shape in a plane direction different from a cross-sectional shape of the unoxidized region in a plane direction; and a plurality of metal electrodes formed in regions on a top face of the mesa not facing the unoxidized region.
    Type: Application
    Filed: March 30, 2011
    Publication date: October 13, 2011
    Applicant: Sony Corporation
    Inventors: Yuji Masui, Takahiro Arakida, Kayoko Kikuchi, Terukazu Naruse, Koichi Kondo, Naoki Jogan