Abstract: A semiconductor device includes a first substrate having a first surface, and a second substrate having a second surface in contact with the first surface. The first substrate includes a first circuit, a first electrode having a first connection end on the first surface, and a first auxiliary electrode having a second connection end on the first surface. The first electrode is connected to the first circuit inside the first substrate, and the first auxiliary electrode is connected to the first electrode. The second substrate includes a second circuit and a second electrode having a third connection end on the second surface. The second electrode is connected to the second circuit. The third connection end is connected directly with the first connection end and the second connection end. The second electrode is connected directly with the first electrode and through the first auxiliary electrode to the first electrode.

Abstract: A semiconductor device includes a first device; and a second device bonded to the first device. The first device includes a plurality of first metal pads provided above a semiconductor substrate with an approximately circular shape; a first circuit coupled to at least one of the plurality of the first metal pads; and a first metal ring provided along an outer circumference of the semiconductor substrate to surround the first circuit. The second device includes a plurality of second metal pads joined to the plurality of the first metal pads, respectively; a second circuit coupled to at least one of the plurality of the second metal pads; and a second metal ring joined to the first metal ring.

Abstract: A semiconductor device of an embodiment includes a first chip having a memory cell array, and a second chip having a control circuit. The first chip includes a substrate, a pad, a first structural body, and a second structural body. The substrate is arranged on the side opposite to a joined face of the first chip joined to the second chip, and includes a first face, a second face, and an opening extending from the second face to the first face in a first region. The memory cell array is provided between the first face and the opposed joined face. The pad is provided in the opening. The first structural body is provided between the first face and the joined face, and is electrically connected to the pad. The second structural body is provided between the first face and the joined face in the first region.

Abstract: A semiconductor device includes a first substrate having a first surface, and a second substrate having a second surface in contact with the first surface. The first substrate includes a first circuit, a first electrode having a first connection end on the first surface, and a first auxiliary electrode having a second connection end on the first surface. The first electrode is connected to the first circuit inside the first substrate, and the first auxiliary electrode is connected to the first electrode. The second substrate includes a second circuit and a second electrode having a third connection end on the second surface. The second electrode is connected to the second circuit. The third connection end is connected directly with the first connection end and the second connection end. The second electrode is connected directly with the first electrode and through the first auxiliary electrode to the first electrode.

Abstract: A semiconductor manufacturing apparatus includes a stage configured to mount a wafer on a mounting surface. A blade is configured to cut an outer circumference portion of the wafer toward the mounting surface. The stage includes a protrusion portion provided at a position corresponding to a first region where a material film is not formed on a first surface of the outer circumference portion of the wafer facing the mounting surface.

Abstract: A semiconductor device of an embodiment includes a first chip having a memory cell array, and a second chip having a control circuit. The first chip includes a substrate, a pad, a first structural body, and a second structural body. The substrate is arranged on the side opposite to a joined face of the first chip joined to the second chip, and includes a first face, a second face, and an opening extending from the second face to the first face in a first region. The memory cell array is provided between the first face and the opposed joined face. The pad is provided in the opening. The first structural body is provided between the first face and the joined face, and is electrically connected to the pad. The second structural body is provided between the first face and the joined face in the first region.

Abstract: In one embodiment, a semiconductor device includes a first film including a plurality of electrode layers and a plurality of insulating layers provided alternately in a first direction, and a first semiconductor layer provided in the first film via a charge storage layer and extending in the first direction. The device further includes a first conductive member provided in the first film and extending in the first direction, and a second semiconductor layer provided on the first film to contact the first semiconductor layer. The second semiconductor layer includes a first surface on a side of the first film, and a second surface on an opposite side of the first surface. The second surface is an uneven face protruding towards the first direction.

Abstract: In one embodiment, a semiconductor device includes a first film including a plurality of electrode layers and a plurality of insulating layers provided alternately in a first direction, and a first semiconductor layer provided in the first film via a charge storage layer and extending in the first direction. The device further includes a first conductive member provided in the first film and extending in the first direction, and a second semiconductor layer provided on the first film to contact the first semiconductor layer. The second semiconductor layer includes a first surface on a side of the first film, and a second surface on an opposite side of the first surface. The second surface is an uneven face protruding towards the first direction.

Abstract: According to one embodiment, the circuit portion includes a transistor provided at a region separated from the first stacked portion in the substrate. The second stacked portion is provided above the circuit portion. The second stacked portion includes a plurality of first layers and a plurality of second layers. The first layers and the second layers include a first layer and a second layer stacked alternately. An insulating layer is provided above the circuit portion and provided above the substrate between the first stacked portion and the second stacked portion. A height of an uppermost first layer of the second stacked portion from a surface of the substrate is substantially equal to a height of an uppermost electrode layer of the first stacked portion from the surface of the substrate, or is higher than the height of the uppermost electrode layer.

Abstract: In a method of forming a mark pattern according to the embodiments, a film to be processed on a substrate is coated with a photosensitive film, and the photosensitive film is irradiated with exposure light via a mask. On the mask, a first circuit pattern having a first transmittance and a mark having a second transmittance and used to measure a superposition between films are arranged. By irradiating with the exposure light, a second circuit pattern having a first film thickness and a mark pattern having a second film thickness thinner than the first film thickness are formed on the substrate.

Abstract: A microstructure body according to an embodiment includes a stacked body. The stacked body includes a plurality of unit structure bodies stacked periodically along a first direction. A configuration of an end portion of the stacked body in a second direction is a stairstep configuration including terraces formed every unit structure body. The second direction intersects the first direction. A first distance in a third direction between end edges of two of the unit structure bodies facing the third direction is shorter than a second distance in the second direction between end edges of the two of the unit structure bodies facing the second direction. The third direction intersects both the first direction and the second direction.

Abstract: In a method of forming a mark pattern according to the embodiments, a film to be processed on a substrate is coated with a photosensitive film, and the photosensitive film is irradiated with exposure light via a mask. On the mask, a first circuit pattern having a first transmittance and a mark having a second transmittance and used to measure a superposition between films are arranged. By irradiating with the exposure light, a second circuit pattern having a first film thickness and a mark pattern having a second film thickness thinner than the first film thickness are formed on the substrate.

Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, which includes thereon a first region where memory elements are arranged and a second region where circuit elements driving the memory elements are arranged. The first region is provided with a stacked body including a plurality of metal films. Further, the stacked body is divided into a plurality of parts by first separation portions extending in a first direction. The second region is provided with an auxiliary pattern, which includes the stacked body together with a separation portion pair including a pair of second separation portions that divide the stacked body. The second separation portions extend in a second direction intersecting with the first direction.

Abstract: A microstructure body according to an embodiment includes a stacked body. The stacked body includes a plurality of unit structure bodies stacked periodically along a first direction. A configuration of an end portion of the stacked body in a second direction is a stairstep configuration including terraces formed every unit structure body. The second direction intersects the first direction. A first distance in a third direction between end edges of two of the unit structure bodies facing the third direction is shorter than a second distance in the second direction between end edges of the two of the unit structure bodies facing the second direction. The third direction intersects both the first direction and the second direction.

Abstract: According to one embodiment, it includes an object film and an opening that is formed in the object film and in which a second taper adjoining a first taper is provided. A step is provided at the boundary between the first taper and the second taper.

Abstract: A nonvolatile semiconductor memory device includes first and second memory blocks which are disposed adjacent to each other in a first direction. The first and second memory blocks each include a plurality of bit lines, a plurality of word lines, which are disposed to extend in a second direction, and a memory cell, which is connected to any of the plurality of word lines. The first memory block includes a first selection gate line which is connected to one end of the memory cell, and the second memory block includes a second selection gate line in the same manner. An end portion of one end of the first selection gate line includes an L-shaped portion, and an end portion of one end of the second selection gate line includes a linear portion. A first contact is disposed on the L-shaped portion of the first selection gate.

Abstract: According to one embodiment, a step difference estimation unit, an assist pattern generation unit, and a spherical aberration conversion unit are installed. The step difference estimation unit estimates step difference of a processing layer. The assist pattern generation unit adds an assist pattern having different sensitivity to spherical aberration in an exposure process to a mask pattern based on the step difference of the processing layer. The spherical aberration conversion unit converts the step difference of the processing layer into the spherical aberration.

Abstract: According to one embodiment, a step difference estimation unit, an assist pattern generation unit, and a spherical aberration conversion unit are installed. The step difference estimation unit estimates step difference of a processing layer. The assist pattern generation unit adds an assist pattern having different sensitivity to spherical aberration in an exposure process to a mask pattern based on the step difference of the processing layer. The spherical aberration conversion unit converts the step difference of the processing layer into the spherical aberration.

Abstract: The semiconductor device manufacturing method comprises the step of transferring patterns formed on a reticle to a semiconductor substrate by an exposure with oblique incidence illumination. In the step of making the exposure with oblique incidence illumination, the exposure is made with an aperture stop 16 including a first ring-shaped aperture 22, and a plurality of second apertures 24a1-24a4 formed around the first ring-shaped aperture 22. The exposure is made with an aperture stop 16 having the first ring-shaped aperture 22 which can transfer patterns arranged at a medium pitch to a relatively large pitch with a relatively high resolution and the second aperture 24a1-24a4 which can transfer patterns arranged at a relatively small pitch with a relatively high resolution, whereby even when the patterns are arranged at various pitch values, the DOF can be surely sufficient, and the patterns can be stably transferred.

Abstract: The semiconductor device manufacturing method comprises the step of transferring patterns formed on a reticle to a semiconductor substrate by an exposure with oblique incidence illumination. In the step of making the exposure with oblique incidence illumination, the exposure is made with an aperture stop 16 including a first ring-shaped aperture 22, and a plurality of second apertures 24a1-24a4 formed around the first ring-shaped aperture 22. The exposure is made with an aperture stop 16 having the first ring-shaped aperture 22 which can transfer patterns arranged at a medium pitch to a relatively large pitch with a relatively high resolution and the second aperture 24a1-24a4 which can transfer patterns arranged at a relatively small pitch with a relatively high resolution, whereby even when the patterns are arranged at various pitch values, the DOF can be surely sufficient, and the patterns can be stably transferred.