Patents by Inventor Yuji Setta

Yuji Setta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220077090
    Abstract: A semiconductor device of an embodiment includes a first chip having a memory cell array, and a second chip having a control circuit. The first chip includes a substrate, a pad, a first structural body, and a second structural body. The substrate is arranged on the side opposite to a joined face of the first chip joined to the second chip, and includes a first face, a second face, and an opening extending from the second face to the first face in a first region. The memory cell array is provided between the first face and the opposed joined face. The pad is provided in the opening. The first structural body is provided between the first face and the joined face, and is electrically connected to the pad. The second structural body is provided between the first face and the joined face in the first region.
    Type: Application
    Filed: June 17, 2021
    Publication date: March 10, 2022
    Applicant: Kioxia Corporation
    Inventor: Yuji SETTA
  • Patent number: 11195849
    Abstract: In one embodiment, a semiconductor device includes a first film including a plurality of electrode layers and a plurality of insulating layers provided alternately in a first direction, and a first semiconductor layer provided in the first film via a charge storage layer and extending in the first direction. The device further includes a first conductive member provided in the first film and extending in the first direction, and a second semiconductor layer provided on the first film to contact the first semiconductor layer. The second semiconductor layer includes a first surface on a side of the first film, and a second surface on an opposite side of the first surface. The second surface is an uneven face protruding towards the first direction.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: December 7, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Yasuhito Yoshimizu, Yuji Setta, Masaru Kito
  • Publication number: 20200303408
    Abstract: In one embodiment, a semiconductor device includes a first film including a plurality of electrode layers and a plurality of insulating layers provided alternately in a first direction, and a first semiconductor layer provided in the first film via a charge storage layer and extending in the first direction. The device further includes a first conductive member provided in the first film and extending in the first direction, and a second semiconductor layer provided on the first film to contact the first semiconductor layer. The second semiconductor layer includes a first surface on a side of the first film, and a second surface on an opposite side of the first surface. The second surface is an uneven face protruding towards the first direction.
    Type: Application
    Filed: September 13, 2019
    Publication date: September 24, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Yasuhito YOSHIMIZU, Yuji SETTA, Masaru KITO
  • Patent number: 9853052
    Abstract: According to one embodiment, the circuit portion includes a transistor provided at a region separated from the first stacked portion in the substrate. The second stacked portion is provided above the circuit portion. The second stacked portion includes a plurality of first layers and a plurality of second layers. The first layers and the second layers include a first layer and a second layer stacked alternately. An insulating layer is provided above the circuit portion and provided above the substrate between the first stacked portion and the second stacked portion. A height of an uppermost first layer of the second stacked portion from a surface of the substrate is substantially equal to a height of an uppermost electrode layer of the first stacked portion from the surface of the substrate, or is higher than the height of the uppermost electrode layer.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: December 26, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yuji Setta
  • Patent number: 9741564
    Abstract: In a method of forming a mark pattern according to the embodiments, a film to be processed on a substrate is coated with a photosensitive film, and the photosensitive film is irradiated with exposure light via a mask. On the mask, a first circuit pattern having a first transmittance and a mark having a second transmittance and used to measure a superposition between films are arranged. By irradiating with the exposure light, a second circuit pattern having a first film thickness and a mark pattern having a second film thickness thinner than the first film thickness are formed on the substrate.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: August 22, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuji Setta, Taketo Kuriyama, Nobuhiro Komine
  • Patent number: 9698157
    Abstract: A microstructure body according to an embodiment includes a stacked body. The stacked body includes a plurality of unit structure bodies stacked periodically along a first direction. A configuration of an end portion of the stacked body in a second direction is a stairstep configuration including terraces formed every unit structure body. The second direction intersects the first direction. A first distance in a third direction between end edges of two of the unit structure bodies facing the third direction is shorter than a second distance in the second direction between end edges of the two of the unit structure bodies facing the second direction. The third direction intersects both the first direction and the second direction.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: July 4, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuko Kono, Takaki Hashimoto, Yuji Setta, Toshiya Kotani, Chikaaki Kodama
  • Publication number: 20160322307
    Abstract: In a method of forming a mark pattern according to the embodiments, a film to be processed on a substrate is coated with a photosensitive film, and the photosensitive film is irradiated with exposure light via a mask. On the mask, a first circuit pattern having a first transmittance and a mark having a second transmittance and used to measure a superposition between films are arranged. By irradiating with the exposure light, a second circuit pattern having a first film thickness and a mark pattern having a second film thickness thinner than the first film thickness are formed on the substrate.
    Type: Application
    Filed: July 30, 2015
    Publication date: November 3, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yuji SETTA, Taketo KURIYAMA, Nobuhiro KOMINE
  • Patent number: 9455271
    Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, which includes thereon a first region where memory elements are arranged and a second region where circuit elements driving the memory elements are arranged. The first region is provided with a stacked body including a plurality of metal films. Further, the stacked body is divided into a plurality of parts by first separation portions extending in a first direction. The second region is provided with an auxiliary pattern, which includes the stacked body together with a separation portion pair including a pair of second separation portions that divide the stacked body. The second separation portions extend in a second direction intersecting with the first direction.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: September 27, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yuji Setta
  • Publication number: 20160268278
    Abstract: A microstructure body according to an embodiment includes a stacked body. The stacked body includes a plurality of unit structure bodies stacked periodically along a first direction. A configuration of an end portion of the stacked body in a second direction is a stairstep configuration including terraces formed every unit structure body. The second direction intersects the first direction. A first distance in a third direction between end edges of two of the unit structure bodies facing the third direction is shorter than a second distance in the second direction between end edges of the two of the unit structure bodies facing the second direction. The third direction intersects both the first direction and the second direction.
    Type: Application
    Filed: August 25, 2015
    Publication date: September 15, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yuko KONO, Takaki Hashimoto, Yuji Setta, Toshiya Kotani, Chikaaki Kodama
  • Publication number: 20150357410
    Abstract: According to one embodiment, it includes an object film and an opening that is formed in the object film and in which a second taper adjoining a first taper is provided. A step is provided at the boundary between the first taper and the second taper.
    Type: Application
    Filed: September 10, 2014
    Publication date: December 10, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takuya MIZUTANI, Yuji SETTA, Kentaro MATSUNAGA
  • Publication number: 20150060975
    Abstract: A nonvolatile semiconductor memory device includes first and second memory blocks which are disposed adjacent to each other in a first direction. The first and second memory blocks each include a plurality of bit lines, a plurality of word lines, which are disposed to extend in a second direction, and a memory cell, which is connected to any of the plurality of word lines. The first memory block includes a first selection gate line which is connected to one end of the memory cell, and the second memory block includes a second selection gate line in the same manner. An end portion of one end of the first selection gate line includes an L-shaped portion, and an end portion of one end of the second selection gate line includes a linear portion. A first contact is disposed on the L-shaped portion of the first selection gate.
    Type: Application
    Filed: February 26, 2014
    Publication date: March 5, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroyuki NITTA, Yusuke OKUMURA, Yuji SETTA
  • Patent number: 8910096
    Abstract: According to one embodiment, a step difference estimation unit, an assist pattern generation unit, and a spherical aberration conversion unit are installed. The step difference estimation unit estimates step difference of a processing layer. The assist pattern generation unit adds an assist pattern having different sensitivity to spherical aberration in an exposure process to a mask pattern based on the step difference of the processing layer. The spherical aberration conversion unit converts the step difference of the processing layer into the spherical aberration.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: December 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yuji Setta
  • Publication number: 20140240683
    Abstract: According to one embodiment, a step difference estimation unit, an assist pattern generation unit, and a spherical aberration conversion unit are installed. The step difference estimation unit estimates step difference of a processing layer. The assist pattern generation unit adds an assist pattern having different sensitivity to spherical aberration in an exposure process to a mask pattern based on the step difference of the processing layer. The spherical aberration conversion unit converts the step difference of the processing layer into the spherical aberration.
    Type: Application
    Filed: July 24, 2013
    Publication date: August 28, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Yuji SETTA
  • Patent number: 8349541
    Abstract: The semiconductor device manufacturing method comprises the step of transferring patterns formed on a reticle to a semiconductor substrate by an exposure with oblique incidence illumination. In the step of making the exposure with oblique incidence illumination, the exposure is made with an aperture stop 16 including a first ring-shaped aperture 22, and a plurality of second apertures 24a1-24a4 formed around the first ring-shaped aperture 22. The exposure is made with an aperture stop 16 having the first ring-shaped aperture 22 which can transfer patterns arranged at a medium pitch to a relatively large pitch with a relatively high resolution and the second aperture 24a1-24a4 which can transfer patterns arranged at a relatively small pitch with a relatively high resolution, whereby even when the patterns are arranged at various pitch values, the DOF can be surely sufficient, and the patterns can be stably transferred.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: January 8, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yuji Setta, Hiroki Futatsuya
  • Patent number: 8349540
    Abstract: The semiconductor device manufacturing method comprises the step of transferring patterns formed on a reticle to a semiconductor substrate by an exposure with oblique incidence illumination. In the step of making the exposure with oblique incidence illumination, the exposure is made with an aperture stop 16 including a first ring-shaped aperture 22, and a plurality of second apertures 24a1-24a4 formed around the first ring-shaped aperture 22. The exposure is made with an aperture stop 16 having the first ring-shaped aperture 22 which can transfer patterns arranged at a medium pitch to a relatively large pitch with a relatively high resolution and the second aperture 24a1-24a4 which can transfer patterns arranged at a relatively small pitch with a relatively high resolution, whereby even when the patterns are arranged at various pitch values, the DOF can be surely sufficient, and the patterns can be stably transferred.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: January 8, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yuji Setta, Hiroki Futatsuya
  • Patent number: 8093156
    Abstract: To provide a method for manufacturing a semiconductor device, which the method is capable of efficient mass production of high-performance semiconductor devices by, upon manufacture of a semiconductor device, eliminating unwanted features (e.g., side lobes) created together with a resist pattern by thickening the resist pattern, to reduce the burden in designing photomasks and to increase depth of focus. The method of the present invention for manufacturing a semiconductor device includes at least: forming a resist pattern on a work surface and applying over a surface of the resist pattern a resist pattern thickening material to thereby thicken the resist pattern to eliminate an unwanted feature created together with the resist pattern.
    Type: Grant
    Filed: January 22, 2007
    Date of Patent: January 10, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yuji Setta, Hajime Yamamoto
  • Publication number: 20110312186
    Abstract: The semiconductor device manufacturing method comprises the step of transferring patterns formed on a reticle to a semiconductor substrate by an exposure with oblique incidence illumination. In the step of making the exposure with oblique incidence illumination, the exposure is made with an aperture stop 16 including a first ring-shaped aperture 22, and a plurality of second apertures 24a1-24a4 formed around the first ring-shaped aperture 22. The exposure is made with an aperture stop 16 having the first ring-shaped aperture 22 which can transfer patterns arranged at a medium pitch to a relatively large pitch with a relatively high resolution and the second aperture 24a1-24a4 which can transfer patterns arranged at a relatively small pitch with a relatively high resolution, whereby even when the patterns are arranged at various pitch values, the DOF can be surely sufficient, and the patterns can be stably transferred.
    Type: Application
    Filed: August 26, 2011
    Publication date: December 22, 2011
    Applicant: Fujitsu Semiconductor Limited
    Inventors: Yuji SETTA, Hiroki Futatsuya
  • Patent number: 8043948
    Abstract: A semiconductor device manufacturing method includes: forming a conductive film over a substrate; forming an assist pattern on the conductive film; forming a metal film to cover the conductive film and the assist pattern; etching back the metal film to form at least one side wall film on a side surface of the assist pattern; removing the assist pattern; forming at least one resist pattern to selectively expose a portion of the conductive film and a portion of the side wall film; performing etching using the resist pattern as a mask to remove the exposed portion of the side wall film; and etching the conductive film using the side wall film as a mask to form a gate electrode and a contact region electrically connected to the gate electrode.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: October 25, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yuji Setta
  • Patent number: 7927764
    Abstract: A method of manufacturing a film pattern includes forming a film over a substrate, applying a photoresist over the film, exposing the photoresist using a first mask pattern including a first mask opening and a second mask opening, and an optical proximity correction being applied only to the first mask opening, exposing the photoresist using a second mask pattern including a third mask opening and a fourth mask opening, an optical proximity correction being applied only to the fourth mask opening.
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: April 19, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yuji Setta
  • Publication number: 20100190327
    Abstract: A semiconductor device manufacturing method includes: forming a conductive film over a substrate; forming an assist pattern on the conductive film; forming a metal film to cover the conductive film and the assist pattern; etching back the metal film to form at least one side wall film on a side surface of the assist pattern; removing the assist pattern; forming at least one resist pattern to selectively expose a portion of the conductive film and a portion of the side wall film; performing etching using the resist pattern as a mask to remove the exposed portion of the side wall film; and etching the conductive film using the side wall film as a mask to form a gate electrode and a contact region electrically connected to the gate electrode.
    Type: Application
    Filed: January 21, 2010
    Publication date: July 29, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Yuji Setta