Patents by Inventor Yuji Shirai

Yuji Shirai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10071219
    Abstract: An anesthetic tank includes an insertion mouth for inserting an injection adapter of an anesthetic container, and a storage portion communicating with the insertion mouth. A volatile anesthetic inside of the anesthetic container is injected into the storage portion. An identifying member is arranged on the outside of the insertion mouth and is rotatable around the center axis of the insertion mouth. The identifying member has key groove formed in the internal surface of an insertion hole for inserting the injection adapter. The key groove are used for identifying the type of the volatile anesthetic in collaboration with keys formed in the injection adapter. A cover member has an opening formed in the position facing the insertion mouth and the insertion hole and presses the peripheral part of the identifying member.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: September 11, 2018
    Assignee: ACOMA MEDICAL INDUSTRY CO., LTD.
    Inventors: Masaki Ito, Hideki Uchida, Kei Shimada, Yuji Shirai, Koji Fujii
  • Publication number: 20180243529
    Abstract: An anesthetic tank includes an insertion mouth for inserting an injection adapter of an anesthetic container, and a storage portion communicating with the insertion mouth. A volatile anesthetic inside of the anesthetic container is injected into the storage portion. An identifying member is arranged on the outside of the insertion mouth and is rotatable around the center axis of the insertion mouth. The identifying member has key groove formed in the internal surface of an insertion hole for inserting the injection adapter. The key groove are used for identifying the type of the volatile anesthetic in collaboration with keys formed in the injection adapter. A cover member has an opening formed in the position facing the insertion mouth and the insertion hole and presses the peripheral part of the identifying member.
    Type: Application
    Filed: April 19, 2017
    Publication date: August 30, 2018
    Inventors: Masaki ITO, Hideki UCHIDA, Kei SHIMADA, Yuji SHIRAI, Koji FUJII
  • Patent number: 9001528
    Abstract: A shielded electronic component including a wiring board, at least one semiconductor chip mounted on a main surface of the wiring board, a sealant which seals the whole of an upper surface of the wiring board, and a nickel (Ni) plating film formed on an upper surface of the sealant is provided. The Ni plating film is formed on a palladium (Pd) pretreatment layer formed on the upper surface of the sealant with using high-pressure CO2 in a state of protecting a back surface of the wiring board, and is electrically connected with an end portion of a ground wiring layer of the wiring board or a ground (GND) connection through-hole connected with the end portion of the ground wiring layer.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: April 7, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Chiko Yorita, Yoshihide Yamaguchi, Yuji Shirai, Yu Hasegawa
  • Patent number: 8763242
    Abstract: In a method of manufacturing a semiconductor device, a second wiring substrate is stacked over a first wiring substrate using a conductive paste, where each wiring substrate has mounted thereon an electronic component. The conductive paste is hardened to form a metal column which forms an electrical connection between the first wiring substrate and the second wiring substrate. The wiring substrates are sealed with a resin. The semiconductor device can be downsized, thinned, and made highly reliable, and its manufacturing cost can be reduced. By using conductive paste for the electrical connection between the wiring substrates, a connecting pitch can be smaller than that in a connecting method of using a solder ball including Cu core, and a connection at low temperature can be achieved. Also, by coating the conductive paste by a print-coating or dispense-coating method, manufacturing is simplified and the manufacturing cost is reduced.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: July 1, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kenya Kawano, Chiko Yorita, Yuji Shirai
  • Patent number: 8742499
    Abstract: In a semiconductor chip in which LDMOSFET elements for power amplifier circuits used for a power amplifier module are formed, a source bump electrode is disposed on an LDMOSFET formation region in which a plurality of source regions, a plurality of drain regions and a plurality of gate electrodes for the LDMOSFET elements are formed. The source bump electrode is formed on a source pad mainly made of aluminum via a source conductor layer which is thicker than the source pad and mainly made of copper. No resin film is interposed between the source bump electrode and the source conductor layer.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: June 3, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shizuki Nakajima, Hiroyuki Nagai, Yuji Shirai, Hirokazu Nakajima, Chushiro Kusano, Yu Hasegawa, Chiko Yorita, Yasuo Osone
  • Publication number: 20120292772
    Abstract: A shielded electronic component including a wiring board, at least one semiconductor chip mounted on a main surface of the wiring board, a sealant which seals the whole of an upper surface of the wiring board, and a nickel (Ni) plating film formed on an upper surface of the sealant is provided. The Ni plating film is formed on a palladium (Pd) pretreatment layer formed on the upper surface of the sealant with using high-pressure CO2 in a state of protecting a back surface of the wiring board, and is electrically connected with an end portion of a ground wiring layer of the wiring board or a ground (GND) connection through-hole connected with the end portion of the ground wiring layer.
    Type: Application
    Filed: July 30, 2012
    Publication date: November 22, 2012
    Inventors: Chiko Yorita, Yoshihide Yamaguchi, Yuji Shirai, Yu Hasegawa
  • Publication number: 20110248389
    Abstract: An upper module board on which an integrated chip component with a low upper temperature limit is mounted and a lower module board on which a heat-generating semiconductor chip, a single chip component and an integrated chip component are mounted are electrically and mechanically connected via a plurality of conductive connecting members, and these are sealed together with mold resin. In such a circumstance, a shield layer made up of a stacked film of a Cu plating film and a Ni plating film is formed on side surfaces of the upper and lower module boards and surfaces (upper and side surfaces) of the mold resin, thereby realizing the electromagnetic wave shield structure.
    Type: Application
    Filed: March 17, 2011
    Publication date: October 13, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Chiko YORITA, Tsutomu HARA, Hiroshi OKABE, Tomonori TANOUE, Yuji SHIRAI
  • Publication number: 20110156225
    Abstract: A semiconductor device achieving both electromagnetic wave shielding property and reliability in a heating process upon mounting electronic components. In the semiconductor device, mount devices 5 and 6 mounted on a main surface of a circuit board 1 are provided, the mount devices 5 and 6 are electrically connected to a wiring pattern 4 at the main surface of the circuit board 1, a sealant 7 of an insulating resin is formed to seal the mount devices 5 and 6, metal particles are applied to a surface of the sealant 7, and the metal particles applied are sintered, thereby forming an electromagnetic shielding layer 2, and electrically connecting the electromagnetic shielding layer 2 to a ground pattern 3 of the circuit board 1.
    Type: Application
    Filed: July 31, 2009
    Publication date: June 30, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroshi Hozoji, Toshiaki Morita, Yusuke Yasuda, Chiko Yorita, Yuji Shirai
  • Publication number: 20110128713
    Abstract: In a semiconductor device in which a plurality of wiring substrates each mounting an electronic component are stacked and sealed by a resin, the semiconductor device can be downsized, thinned, and highly reliable, and its manufacturing cost can be reduced. By using a metal paste for electrical connection between the stacked lower-layer side wiring substrate and upper-layer side wiring substrate, a connecting pitch can be smaller than that in a connecting method of using a solder ball including Cu core, and the connection at low temperature can be achieved. Also, by coating a metal paste by a print-coating method or a dispense-coating method, manufacturing steps are simplified, so that the manufacturing cost is reduced.
    Type: Application
    Filed: November 30, 2010
    Publication date: June 2, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Kenya KAWANO, Chiko YORITA, Yuji SHIRAI
  • Publication number: 20100230789
    Abstract: A technology is provided which allows a reduction in the size of a semiconductor device without degrading an electromagnetic shielding effect and reliability against reflow heating. After a plurality of components are mounted over a component mounting surface of a module substrate, a resin is formed so as to cover the mounted components. Further, over surfaces (upper and side surfaces) of the resin, a shield layer including a laminated film of a Cu plating film and an Ni plating film is formed. In the shield layer, a plurality of microchannel cracks are formed randomly along grain boundaries and in a net-like configuration without being coupled to each other in a straight line, and form a plurality of paths extending from the resin to a surface of the shield layer by the microchannel cracks.
    Type: Application
    Filed: March 15, 2010
    Publication date: September 16, 2010
    Inventors: Chiko Yorita, Yuji Shirai, Hirokazu Nakajima, Hiroshi Ozaku, Tomonori Tanoue, Hiroshi Okabe, Tsutomu Hara
  • Publication number: 20100172116
    Abstract: A shielded electronic component including a wiring board, at least one semiconductor chip mounted on a main surface of the wiring board, a sealant which seals the whole of an upper surface of the wiring board, and a nickel (Ni) plating film formed on an upper surface of the sealant is provided. The Ni plating film is formed on a palladium (Pd) pretreatment layer formed on the upper surface of the sealant with using high-pressure CO2 in a state of protecting a back surface of the wiring board, and is electrically connected with an end portion of a ground wiring layer of the wiring board or a ground (GND) connection through-hole connected with the end portion of the ground wiring layer.
    Type: Application
    Filed: November 5, 2009
    Publication date: July 8, 2010
    Inventors: Chiko Yorita, Yoshihide Yamaguchi, Yuji Shirai, Yu Hasegawa
  • Publication number: 20100109052
    Abstract: In a semiconductor chip in which LDMOSFET elements for power amplifier circuits used for a power amplifier module are formed, a source bump electrode is disposed on an LDMOSFET formation region in which a plurality of source regions, a plurality of drain regions and a plurality of gate electrodes for the LDMOSFET elements are formed. The source bump electrode is formed on a source pad mainly made of aluminum via a source conductor layer which is thicker than the source pad and mainly made of copper. No resin film is interposed between the source bump electrode and the source conductor layer.
    Type: Application
    Filed: October 29, 2009
    Publication date: May 6, 2010
    Inventors: Shizuki NAKAJIMA, Hiroyuki NAGAI, Yuji SHIRAI, Hirokazu NAKEJIMA, Chushiro KUSANO, Yu HASEGAWA, Chiko YORITA, Yasuo OSONE
  • Patent number: 7656030
    Abstract: Heating elements different in heat generating timing are laminated in a stacked state, and the heating element close to a wiring substrate is allowed to function as a heat diffusion plate for another heating element.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: February 2, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Yasuo Osone, Kenya Kawano, Chiko Yorita, Yu Hasegawa, Yuji Shirai, Naotaka Tanaka, Seiichi Tomoi, Hiroshi Okabe
  • Patent number: 7583163
    Abstract: A technique capable of integrally forming SMR type acoustic wave filters corresponding to multiple bands on the same chip at low cost is provided. In SMR type acoustic wave filters including multiple bandpass filters corresponding to multiple bands formed over the same die (substrate), acoustic multilayer films are formed without or with a minimum number of masks and piezoelectric thin films having different thicknesses for respective bands are collectively formed. For example, after the acoustic multilayer films (low acoustic impedance layers and high acoustic impedance layers) are formed in a deep groove in a terrace paddy field shape over the die in a maskless manner, the piezoelectric thin films are c-axis-oriented and grown, and are polished by CMP method or the like to be adjusted in a thickness for respective bands, and therefore, the SMR type acoustic wave filters for multiple bands are formed over the same chip.
    Type: Grant
    Filed: August 10, 2007
    Date of Patent: September 1, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Yasuo Osone, Chiko Yorita, Yuji Shirai, Seiichi Tomoi
  • Patent number: 7554193
    Abstract: A semiconductor device capable of reducing the thermal resistance in a flip chip packaging structure while achieving both the high radiation performance and manufacturing readiness without increasing the manufacturing cost is provided. In a semiconductor device having a semiconductor circuit for power amplification and a control circuit of the semiconductor circuit laminated on a multilayer circuit board, the semiconductor circuit for power amplification and the control circuit are aligned in parallel on the same semiconductor element, and the semiconductor element is flip-chip connected on the multilayer circuit board. Further, a second semiconductor element mounted in addition to the first semiconductor element and all components and submodules are flip-chip connected. Also, a plurality of bumps are united in order to improve the radiation performance and thermal vias of the multilayer circuit board are formed in second and lower layers of the wiring layers in the multilayer circuit board.
    Type: Grant
    Filed: August 16, 2006
    Date of Patent: June 30, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Yasuo Osone, Chiko Yorita, Kenya Kawano, Yu Hasegawa, Yuji Shirai, Seiichi Tomoi, Tsuneo Endou, Satoru Konishi, Hirokazu Nakajima
  • Publication number: 20080129412
    Abstract: A technique capable of integrally forming SMR type acoustic wave filters corresponding to multiple bands on the same chip at low cost is provided. In SMR type acoustic wave filters including multiple bandpass filters corresponding to multiple bands formed over the same die (substrate), acoustic multilayer films are formed without or with a minimum number of masks and piezoelectric thin films having different thicknesses for respective bands are collectively formed. For example, after the acoustic multilayer films (low acoustic impedance layers and high acoustic impedance layers) are formed in a deep groove in a terrace paddy field shape over the die in a maskless manner, the piezoelectric thin films are c-axis-oriented and grown, and are polished by CMP method or the like to be adjusted in a thickness for respective bands, and therefore, the SMR type acoustic wave filters for multiple bands are formed over the same chip.
    Type: Application
    Filed: August 10, 2007
    Publication date: June 5, 2008
    Applicant: Renesas Technology Corp.
    Inventors: Yasuo Osone, Chiko Yorita, Yuji Shirai, Seiichi Tomoi
  • Publication number: 20070176298
    Abstract: Heating elements different in heat generating timing are laminated in a stacked state, and the heating element close to a wiring substrate is allowed to function as a heat diffusion plate for another heating element.
    Type: Application
    Filed: January 10, 2007
    Publication date: August 2, 2007
    Applicants: Hitachi, Ltd., Renesas Technology Corp.
    Inventors: Yasuo Osone, Kenya Kawano, Chiko Yorita, Yu Hasegawa, Yuji Shirai, Naotaka Tanaka, Seiichi Tomoi, Hiroshi Okabe
  • Publication number: 20070040255
    Abstract: A semiconductor device capable of reducing the thermal resistance in a flip chip packaging structure while achieving both the high radiation performance and manufacturing readiness without increasing the manufacturing cost is provided. In a semiconductor device having a semiconductor circuit for power amplification and a control circuit of the semiconductor circuit laminated on a multilayer circuit board, the semiconductor circuit for power amplification and the control circuit are aligned in parallel on the same semiconductor element, and the semiconductor element is flip-chip connected on the multilayer circuit board. Further, a second semiconductor element mounted in addition to the first semiconductor element and all components and submodules are flip-chip connected. Also, a plurality of bumps are united in order to improve the radiation performance and thermal vias of the multilayer circuit board are formed in second and lower layers of the wiring layers in the multilayer circuit board.
    Type: Application
    Filed: August 16, 2006
    Publication date: February 22, 2007
    Inventors: Yasuo Osone, Chiko Yorita, Kenya Kawano, Yu Hasegawa, Yuji Shirai, Seiichi Tomoi, Tsuneo Endou, Satoru Konishi, Hirokazu Nakajima
  • Patent number: 6946327
    Abstract: A semiconductor integrated circuit device includes a semiconductor substrate, a circuit element formed on one major surface of the semiconductor substrate and constituting an integrated circuit having a plurality of functions or a plurality of characteristics, an internal connection terminal, connected to the integrated circuit, for selecting one of the plurality of functions or one of the characteristics in the integrated circuit, an insulating layer covering the internal connection terminal such that the internal connection terminal is selectively exposed, and an external connection terminal arranged on the insulating layer. One of the plurality of functions or one of the plurality of characteristics is selected by a connection state between the internal connection terminal and the external connection terminal.
    Type: Grant
    Filed: February 5, 2004
    Date of Patent: September 20, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Toshio Miyamoto, Ichiro Anjo, Asao Nishimura, Mitsuaki Katagiri, Yuji Shirai, Yoshihide Yamaguchi
  • Patent number: 6867123
    Abstract: A semiconductor wafer which has finished formation of a relocating wiring layer thereon is stored and after determination of a design, solder bumps are formed over bump lands (one end of the relocating wiring layer) in accordance with a pattern which differs with a design, whereby a function or characteristic depending on the design is selected. The semiconductor wafer is then cut into a plurality of semiconductor chips, whereby a wafer level CSP is available.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: March 15, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Mitsuaki Katagiri, Yuji Shirai, Kunihiko Nishi, Takehiro Ohnishi