Patents by Inventor Yuji Shirai
Yuji Shirai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11929589Abstract: A light-emitting component includes: a substrate; plural light-emitting elements that are disposed on the substrate and that emit light in a direction intersecting with a surface of the substrate; and plural thyristors that are stacked on the plural light-emitting elements and that are turned ON to drive the corresponding light-emitting elements so that the light-emitting elements emit light or an amount of light emitted from the light-emitting elements is increased. Each of the plural light-emitting elements includes a current confinement region which is oxidized via a hole provided in a multilayer structure. The multilayer structure is constituted by a corresponding light-emitting element and a corresponding thyristor.Type: GrantFiled: December 20, 2020Date of Patent: March 12, 2024Assignee: FUJIFILM Business Innovation Corp.Inventors: Takashi Kondo, Michiaki Murata, Kenichi Ono, Masahiro Yoshikawa, Takehito Hikichi, Yuji Shirai
-
Publication number: 20210305771Abstract: A light-emitting component includes: a substrate; plural light-emitting elements that are disposed on the substrate and that emit light in a direction intersecting with a surface of the substrate; and plural thyristors that are stacked on the plural light-emitting elements and that are turned ON to drive the corresponding light-emitting elements so that the light-emitting elements emit light or an amount of light emitted from the light-emitting elements is increased. Each of the plural light-emitting elements includes a current confinement region which is oxidized via a hole provided in a multilayer structure. The multilayer structure is constituted by a corresponding light-emitting element and a corresponding thyristor.Type: ApplicationFiled: December 20, 2020Publication date: September 30, 2021Applicant: FUJIFILM Business Innovation Corp.Inventors: Takashi KONDO, Michiaki MURATA, Kenichi ONO, Masahiro YOSHIKAWA, Takehito HIKICHI, Yuji SHIRAI
-
Patent number: 10071219Abstract: An anesthetic tank includes an insertion mouth for inserting an injection adapter of an anesthetic container, and a storage portion communicating with the insertion mouth. A volatile anesthetic inside of the anesthetic container is injected into the storage portion. An identifying member is arranged on the outside of the insertion mouth and is rotatable around the center axis of the insertion mouth. The identifying member has key groove formed in the internal surface of an insertion hole for inserting the injection adapter. The key groove are used for identifying the type of the volatile anesthetic in collaboration with keys formed in the injection adapter. A cover member has an opening formed in the position facing the insertion mouth and the insertion hole and presses the peripheral part of the identifying member.Type: GrantFiled: April 19, 2017Date of Patent: September 11, 2018Assignee: ACOMA MEDICAL INDUSTRY CO., LTD.Inventors: Masaki Ito, Hideki Uchida, Kei Shimada, Yuji Shirai, Koji Fujii
-
Publication number: 20180243529Abstract: An anesthetic tank includes an insertion mouth for inserting an injection adapter of an anesthetic container, and a storage portion communicating with the insertion mouth. A volatile anesthetic inside of the anesthetic container is injected into the storage portion. An identifying member is arranged on the outside of the insertion mouth and is rotatable around the center axis of the insertion mouth. The identifying member has key groove formed in the internal surface of an insertion hole for inserting the injection adapter. The key groove are used for identifying the type of the volatile anesthetic in collaboration with keys formed in the injection adapter. A cover member has an opening formed in the position facing the insertion mouth and the insertion hole and presses the peripheral part of the identifying member.Type: ApplicationFiled: April 19, 2017Publication date: August 30, 2018Inventors: Masaki ITO, Hideki UCHIDA, Kei SHIMADA, Yuji SHIRAI, Koji FUJII
-
Patent number: 9001528Abstract: A shielded electronic component including a wiring board, at least one semiconductor chip mounted on a main surface of the wiring board, a sealant which seals the whole of an upper surface of the wiring board, and a nickel (Ni) plating film formed on an upper surface of the sealant is provided. The Ni plating film is formed on a palladium (Pd) pretreatment layer formed on the upper surface of the sealant with using high-pressure CO2 in a state of protecting a back surface of the wiring board, and is electrically connected with an end portion of a ground wiring layer of the wiring board or a ground (GND) connection through-hole connected with the end portion of the ground wiring layer.Type: GrantFiled: July 30, 2012Date of Patent: April 7, 2015Assignee: Renesas Electronics CorporationInventors: Chiko Yorita, Yoshihide Yamaguchi, Yuji Shirai, Yu Hasegawa
-
Patent number: 8763242Abstract: In a method of manufacturing a semiconductor device, a second wiring substrate is stacked over a first wiring substrate using a conductive paste, where each wiring substrate has mounted thereon an electronic component. The conductive paste is hardened to form a metal column which forms an electrical connection between the first wiring substrate and the second wiring substrate. The wiring substrates are sealed with a resin. The semiconductor device can be downsized, thinned, and made highly reliable, and its manufacturing cost can be reduced. By using conductive paste for the electrical connection between the wiring substrates, a connecting pitch can be smaller than that in a connecting method of using a solder ball including Cu core, and a connection at low temperature can be achieved. Also, by coating the conductive paste by a print-coating or dispense-coating method, manufacturing is simplified and the manufacturing cost is reduced.Type: GrantFiled: November 30, 2010Date of Patent: July 1, 2014Assignee: Renesas Electronics CorporationInventors: Kenya Kawano, Chiko Yorita, Yuji Shirai
-
Patent number: 8742499Abstract: In a semiconductor chip in which LDMOSFET elements for power amplifier circuits used for a power amplifier module are formed, a source bump electrode is disposed on an LDMOSFET formation region in which a plurality of source regions, a plurality of drain regions and a plurality of gate electrodes for the LDMOSFET elements are formed. The source bump electrode is formed on a source pad mainly made of aluminum via a source conductor layer which is thicker than the source pad and mainly made of copper. No resin film is interposed between the source bump electrode and the source conductor layer.Type: GrantFiled: October 29, 2009Date of Patent: June 3, 2014Assignee: Murata Manufacturing Co., Ltd.Inventors: Shizuki Nakajima, Hiroyuki Nagai, Yuji Shirai, Hirokazu Nakajima, Chushiro Kusano, Yu Hasegawa, Chiko Yorita, Yasuo Osone
-
Publication number: 20120292772Abstract: A shielded electronic component including a wiring board, at least one semiconductor chip mounted on a main surface of the wiring board, a sealant which seals the whole of an upper surface of the wiring board, and a nickel (Ni) plating film formed on an upper surface of the sealant is provided. The Ni plating film is formed on a palladium (Pd) pretreatment layer formed on the upper surface of the sealant with using high-pressure CO2 in a state of protecting a back surface of the wiring board, and is electrically connected with an end portion of a ground wiring layer of the wiring board or a ground (GND) connection through-hole connected with the end portion of the ground wiring layer.Type: ApplicationFiled: July 30, 2012Publication date: November 22, 2012Inventors: Chiko Yorita, Yoshihide Yamaguchi, Yuji Shirai, Yu Hasegawa
-
Publication number: 20110248389Abstract: An upper module board on which an integrated chip component with a low upper temperature limit is mounted and a lower module board on which a heat-generating semiconductor chip, a single chip component and an integrated chip component are mounted are electrically and mechanically connected via a plurality of conductive connecting members, and these are sealed together with mold resin. In such a circumstance, a shield layer made up of a stacked film of a Cu plating film and a Ni plating film is formed on side surfaces of the upper and lower module boards and surfaces (upper and side surfaces) of the mold resin, thereby realizing the electromagnetic wave shield structure.Type: ApplicationFiled: March 17, 2011Publication date: October 13, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Chiko YORITA, Tsutomu HARA, Hiroshi OKABE, Tomonori TANOUE, Yuji SHIRAI
-
Publication number: 20110156225Abstract: A semiconductor device achieving both electromagnetic wave shielding property and reliability in a heating process upon mounting electronic components. In the semiconductor device, mount devices 5 and 6 mounted on a main surface of a circuit board 1 are provided, the mount devices 5 and 6 are electrically connected to a wiring pattern 4 at the main surface of the circuit board 1, a sealant 7 of an insulating resin is formed to seal the mount devices 5 and 6, metal particles are applied to a surface of the sealant 7, and the metal particles applied are sintered, thereby forming an electromagnetic shielding layer 2, and electrically connecting the electromagnetic shielding layer 2 to a ground pattern 3 of the circuit board 1.Type: ApplicationFiled: July 31, 2009Publication date: June 30, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hiroshi Hozoji, Toshiaki Morita, Yusuke Yasuda, Chiko Yorita, Yuji Shirai
-
Publication number: 20110128713Abstract: In a semiconductor device in which a plurality of wiring substrates each mounting an electronic component are stacked and sealed by a resin, the semiconductor device can be downsized, thinned, and highly reliable, and its manufacturing cost can be reduced. By using a metal paste for electrical connection between the stacked lower-layer side wiring substrate and upper-layer side wiring substrate, a connecting pitch can be smaller than that in a connecting method of using a solder ball including Cu core, and the connection at low temperature can be achieved. Also, by coating a metal paste by a print-coating method or a dispense-coating method, manufacturing steps are simplified, so that the manufacturing cost is reduced.Type: ApplicationFiled: November 30, 2010Publication date: June 2, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Kenya KAWANO, Chiko YORITA, Yuji SHIRAI
-
Publication number: 20100230789Abstract: A technology is provided which allows a reduction in the size of a semiconductor device without degrading an electromagnetic shielding effect and reliability against reflow heating. After a plurality of components are mounted over a component mounting surface of a module substrate, a resin is formed so as to cover the mounted components. Further, over surfaces (upper and side surfaces) of the resin, a shield layer including a laminated film of a Cu plating film and an Ni plating film is formed. In the shield layer, a plurality of microchannel cracks are formed randomly along grain boundaries and in a net-like configuration without being coupled to each other in a straight line, and form a plurality of paths extending from the resin to a surface of the shield layer by the microchannel cracks.Type: ApplicationFiled: March 15, 2010Publication date: September 16, 2010Inventors: Chiko Yorita, Yuji Shirai, Hirokazu Nakajima, Hiroshi Ozaku, Tomonori Tanoue, Hiroshi Okabe, Tsutomu Hara
-
Publication number: 20100172116Abstract: A shielded electronic component including a wiring board, at least one semiconductor chip mounted on a main surface of the wiring board, a sealant which seals the whole of an upper surface of the wiring board, and a nickel (Ni) plating film formed on an upper surface of the sealant is provided. The Ni plating film is formed on a palladium (Pd) pretreatment layer formed on the upper surface of the sealant with using high-pressure CO2 in a state of protecting a back surface of the wiring board, and is electrically connected with an end portion of a ground wiring layer of the wiring board or a ground (GND) connection through-hole connected with the end portion of the ground wiring layer.Type: ApplicationFiled: November 5, 2009Publication date: July 8, 2010Inventors: Chiko Yorita, Yoshihide Yamaguchi, Yuji Shirai, Yu Hasegawa
-
Publication number: 20100109052Abstract: In a semiconductor chip in which LDMOSFET elements for power amplifier circuits used for a power amplifier module are formed, a source bump electrode is disposed on an LDMOSFET formation region in which a plurality of source regions, a plurality of drain regions and a plurality of gate electrodes for the LDMOSFET elements are formed. The source bump electrode is formed on a source pad mainly made of aluminum via a source conductor layer which is thicker than the source pad and mainly made of copper. No resin film is interposed between the source bump electrode and the source conductor layer.Type: ApplicationFiled: October 29, 2009Publication date: May 6, 2010Inventors: Shizuki NAKAJIMA, Hiroyuki NAGAI, Yuji SHIRAI, Hirokazu NAKEJIMA, Chushiro KUSANO, Yu HASEGAWA, Chiko YORITA, Yasuo OSONE
-
Patent number: 7656030Abstract: Heating elements different in heat generating timing are laminated in a stacked state, and the heating element close to a wiring substrate is allowed to function as a heat diffusion plate for another heating element.Type: GrantFiled: January 10, 2007Date of Patent: February 2, 2010Assignee: Renesas Technology Corp.Inventors: Yasuo Osone, Kenya Kawano, Chiko Yorita, Yu Hasegawa, Yuji Shirai, Naotaka Tanaka, Seiichi Tomoi, Hiroshi Okabe
-
Patent number: 7583163Abstract: A technique capable of integrally forming SMR type acoustic wave filters corresponding to multiple bands on the same chip at low cost is provided. In SMR type acoustic wave filters including multiple bandpass filters corresponding to multiple bands formed over the same die (substrate), acoustic multilayer films are formed without or with a minimum number of masks and piezoelectric thin films having different thicknesses for respective bands are collectively formed. For example, after the acoustic multilayer films (low acoustic impedance layers and high acoustic impedance layers) are formed in a deep groove in a terrace paddy field shape over the die in a maskless manner, the piezoelectric thin films are c-axis-oriented and grown, and are polished by CMP method or the like to be adjusted in a thickness for respective bands, and therefore, the SMR type acoustic wave filters for multiple bands are formed over the same chip.Type: GrantFiled: August 10, 2007Date of Patent: September 1, 2009Assignee: Renesas Technology Corp.Inventors: Yasuo Osone, Chiko Yorita, Yuji Shirai, Seiichi Tomoi
-
Patent number: 7554193Abstract: A semiconductor device capable of reducing the thermal resistance in a flip chip packaging structure while achieving both the high radiation performance and manufacturing readiness without increasing the manufacturing cost is provided. In a semiconductor device having a semiconductor circuit for power amplification and a control circuit of the semiconductor circuit laminated on a multilayer circuit board, the semiconductor circuit for power amplification and the control circuit are aligned in parallel on the same semiconductor element, and the semiconductor element is flip-chip connected on the multilayer circuit board. Further, a second semiconductor element mounted in addition to the first semiconductor element and all components and submodules are flip-chip connected. Also, a plurality of bumps are united in order to improve the radiation performance and thermal vias of the multilayer circuit board are formed in second and lower layers of the wiring layers in the multilayer circuit board.Type: GrantFiled: August 16, 2006Date of Patent: June 30, 2009Assignee: Renesas Technology Corp.Inventors: Yasuo Osone, Chiko Yorita, Kenya Kawano, Yu Hasegawa, Yuji Shirai, Seiichi Tomoi, Tsuneo Endou, Satoru Konishi, Hirokazu Nakajima
-
Publication number: 20080129412Abstract: A technique capable of integrally forming SMR type acoustic wave filters corresponding to multiple bands on the same chip at low cost is provided. In SMR type acoustic wave filters including multiple bandpass filters corresponding to multiple bands formed over the same die (substrate), acoustic multilayer films are formed without or with a minimum number of masks and piezoelectric thin films having different thicknesses for respective bands are collectively formed. For example, after the acoustic multilayer films (low acoustic impedance layers and high acoustic impedance layers) are formed in a deep groove in a terrace paddy field shape over the die in a maskless manner, the piezoelectric thin films are c-axis-oriented and grown, and are polished by CMP method or the like to be adjusted in a thickness for respective bands, and therefore, the SMR type acoustic wave filters for multiple bands are formed over the same chip.Type: ApplicationFiled: August 10, 2007Publication date: June 5, 2008Applicant: Renesas Technology Corp.Inventors: Yasuo Osone, Chiko Yorita, Yuji Shirai, Seiichi Tomoi
-
Publication number: 20070176298Abstract: Heating elements different in heat generating timing are laminated in a stacked state, and the heating element close to a wiring substrate is allowed to function as a heat diffusion plate for another heating element.Type: ApplicationFiled: January 10, 2007Publication date: August 2, 2007Applicants: Hitachi, Ltd., Renesas Technology Corp.Inventors: Yasuo Osone, Kenya Kawano, Chiko Yorita, Yu Hasegawa, Yuji Shirai, Naotaka Tanaka, Seiichi Tomoi, Hiroshi Okabe
-
Publication number: 20070040255Abstract: A semiconductor device capable of reducing the thermal resistance in a flip chip packaging structure while achieving both the high radiation performance and manufacturing readiness without increasing the manufacturing cost is provided. In a semiconductor device having a semiconductor circuit for power amplification and a control circuit of the semiconductor circuit laminated on a multilayer circuit board, the semiconductor circuit for power amplification and the control circuit are aligned in parallel on the same semiconductor element, and the semiconductor element is flip-chip connected on the multilayer circuit board. Further, a second semiconductor element mounted in addition to the first semiconductor element and all components and submodules are flip-chip connected. Also, a plurality of bumps are united in order to improve the radiation performance and thermal vias of the multilayer circuit board are formed in second and lower layers of the wiring layers in the multilayer circuit board.Type: ApplicationFiled: August 16, 2006Publication date: February 22, 2007Inventors: Yasuo Osone, Chiko Yorita, Kenya Kawano, Yu Hasegawa, Yuji Shirai, Seiichi Tomoi, Tsuneo Endou, Satoru Konishi, Hirokazu Nakajima