Abstract: A semiconductor integrated circuit device includes a semiconductor substrate, a circuit element formed on one major surface of the semiconductor substrate and constituting an integrated circuit having a plurality of functions or a plurality of characteristics, an internal connection terminal, connected to the integrated circuit, for selecting one of the plurality of functions or one of the characteristics in the integrated circuit, an insulating layer covering the internal connection terminal such that the internal connection terminal is selectively exposed, and an external connection terminal arranged on the insulating layer. One of the plurality of functions or one of the plurality of characteristics is selected by a connection state between the internal connection terminal and the external connection terminal.

Abstract: A semiconductor wafer which has finished formation of a relocating wiring layer thereon is stored and after determination of a design, solder bumps are formed over bump lands (one end of the relocating wiring layer) in accordance with a pattern which differs with a design, whereby a function or characteristic depending on the design is selected. The semiconductor wafer is then cut into a plurality of semiconductor chips, whereby a wafer level CSP is available.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate, a circuit element formed on one major surface of the semiconductor substrate and constituting an integrated circuit having a plurality of functions or a plurality of characteristics, an internal connection terminal, connected to the integrated circuit, for selecting one of the plurality of functions or one of the characteristics in the integrated circuit, an insulating layer covering the internal connection terminal such that the internal connection terminal is selectively exposed, and an external connection terminal arranged on the insulating layer. One of the plurality of functions or one of the plurality of characteristics is selected by a connection state between the internal connection terminal and the external connection terminal.

Abstract: With respect to two types of chips to be mounted on a main surface of a package substrate, the ratio of chip area to the number of terminals of one chip and that of the other chip are compared with each other and the chip smaller in the ratio is mounted by the wire bonding method, while the chip larger in the ratio is mounted by the flip-chip method. It is possible to reduce the cost of manufacturing a multi-chip module wherein plural types of chips having different terminal pitches are mounted on a wiring substrate.

Abstract: With respect to two types of chips to be mounted on a main surface of a package substrate, the ratio of chip area to the number of terminals of one chip and that of the other chip are compared with each other and the chip smaller in the ratio is mounted by the wire bonding method, while the chip larger in the ratio is mounted by the flip-chip method. It is possible to reduce the cost of manufacturing a multi-chip module wherein plural types of chips having different terminal pitches are mounted on a wiring substrate.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate, a circuit element formed on one major surface of the semiconductor substrate and constituting an integrated circuit having a plurality of functions or a plurality of characteristics, an internal connection terminal, connected to the integrated circuit, for selecting one of the plurality of functions or one of the characteristics in the integrated circuit, an insulating layer covering the internal connection terminal such that the internal connection terminal is selectively exposed, and an external connection terminal arranged on the insulating layer. One of the plurality of functions or one of the plurality of characteristics is selected by a connection state between the internal connection terminal and the external connection terminal.

Abstract: A semiconductor wafer which has finished formation of a relocating wiring layer thereon is stored and after determination of a design, solder bumps are formed over bump lands (one end of the relocating wiring layer) in accordance with a pattern which differs with a design, whereby a function or characteristic depending on the design is selected. The semiconductor wafer is then cut into a plurality of semiconductor chips, whereby a wafer level CSP is available.

Abstract: With respect to two types of chips to be mounted on a main surface of a package substrate, the ratio of chip area to the number of terminals of one chip and that of the other chip are compared with each other and the chip smaller in the ratio is mounted by the wire bonding method, while the chip larger in the ratio is mounted by the flip-chip method. It is possible to reduce the cost of manufacturing a multi-chip module wherein plural types of chips having different terminal pitches are mounted on a wiring substrate.

Abstract: With respect to two types of chips to be mounted on a main surface of a package substrate, the ratio of chip area to the number of terminals of one chip and that of the other chip are compared with each other and the chip smaller in the ratio is mounted by the wire bonding method, while the chip larger in the ratio is mounted by the flip-chip method. It is possible to reduce the cost of manufacturing a multi-chip module wherein plural types of chips having different terminal pitches are mounted on a wiring substrate.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate, a circuit element formed on one major surface of the semiconductor substrate and constituting an integrated circuit having a plurality of functions or a plurality of characteristics, an internal connection terminal, connected to the integrated circuit, for selecting one of the plurality of functions or one of the characteristics in the integrated circuit, an insulating layer covering the internal connection terminal such that the internal connection terminal is selectively exposed, and an external connection terminal arranged on the insulating layer. One of the plurality of functions or one of the plurality of characteristics is selected by a connection state between the internal connection terminal and the external connection terminal.

Abstract: A molded semiconductor device has a plurality of slender leads formed with a sealing strip connecting them together to prevent the molding material from leaking out between the leads. Specifically, the sealing strip comprising an adhesive and an electrically insulating material is applied to the leads substantially perpendicular to the lengthwise direction of the leads. The strip is place such that an inner edge thereof substantially lies on a boundary line or inside where the molding terminates. The strip is then thrust into spaces formed between the leads. Thereafter the semiconductor chip is connected to the leads, the semiconductor chip and the leads are placed in a molding unit, the strip serving to block the molding material leaking outside the molding unit.

Abstract: A semiconductor circuit device includes a multi-layered substrate comprising a plurality of signal lines sandwiched between a power source line and a ground line, with insulation layers formed therebetween to reduce fluctuation of a ground line potential at the time of simultaneous switching of the signal lines and to increase the operational speed. The signal lines provides bidirectional current paths and is disposed between the current source line and the ground line. The multi-layered substrate is formed around a semiconductor pellet. Electrode pads are formed on the insulation layer over the ground line on the same level as the signal lines and generally on the same level as the main surface of the semiconductor pellet where electrodes pads are formed. Bonding wires are used to electrically connect the electrode pads on the pellet and the electrodes formed on the insulation layer.

Abstract: Disclosed is an LSI package cooling heat sink having a heat diffusion plate and thin wire fins joined to the heat diffusion plate. The heat sink is mounted on an LSI package and the LSI package is cooled by the flowing of fluid through the thin wire fins. The wire fins are made of a net formed of longitudinal thin wires intersecting with horizontal thin wires. The net is formed to continuous rectangular shapes or a swirl shape and joined to the heat diffusion plate. The net is constituted so that the number of the thin wires vertical to the heat diffusion plate is larger than the number of the thin wires parallel thereto and the net is joined to the heat diffusion plate by brazing, diffusion joint, pressure welding or the like.

Abstract: A semiconductor apparatus comprises a heat diffusing plate and a surface installing printed board. A semiconductor device of a high heat generation is installed on the heat diffusing plate. A surface installing package and chip parts are installed on both surfaces of the printed board. A through hole is formed at the center of the printed board so that the semiconductor device is located at the center. The heat diffusing plate on which the semiconductor device has been installed and the surface installing printed board are connected and integrated.

Abstract: An LSI cooling apparatus having various structures is used in electronic devices such as computer systems. In particular, the LSI cooling of apparatus is suitable for cooling of LSIs having high heat generating densities. In a cooling apparatus of the present invention, a heat sink is constructed to be small in pressure loss and excellent in cooling performance. This is because the heat sink comprises thin wire fins so set that the Reynold's number may not exceed 40. As a result, LSIs generating a large amount of heat can be cooled. Further, a heat sink having rigidity can be obtained by disposing wide-width wire drawn substances in thin wires or by using supports. Further, a computer comprising LSIs equipped with heat sinks can cope with various cooling air sending methods and it can be cooled with low noises.

Abstract: A fuzzy logic circuit comprising a current mirror comprising an FET, a first input current source connected to the input side of the current mirror, a second input current source, a wired OR connected at its input side to the output side of the current mirror and to the second input current source, and an output terminal connected to the output side of the wired OR.

Abstract: A fuzzy logic circuit comprising a current mirror comprising an FET, a first input current source connected to the input side of the current mirror, a second input current source, a wired OR connected at its input side to the output side of the current mirror and to the second input current source, and an output terminal connected to the output side of the wired OR.

Abstract: A wire bonding apparatus which can variously change the shape of a loop of a bonding wire and can restrict the loop shape in accordance with specifications of an article being wire bonded. In the wire bonding apparatus, a wire guide unit moving both vertically and transversely, independently of a bonding tool, is disposed in proximity of the bonding tool which moves relative to the article to be wire bonded and which connects the wire between a first bonding region and the second bonding region. A mechanism is provided which changes the shape of the loop of the bonding wire when the wire guide unit moves vertically and transversely.