Patents by Inventor Yuji Suwa

Yuji Suwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090001361
    Abstract: The present invention provides a method of manufacturing a thin-film transistor device. This method enables improvement in performance of a complementary TFT circuit incorporated in a thin- and light-weighted image display device or a flexible electronic device and also enables reduction of power consumption and reduction of manufacturing cost of the circuit. Further in the method, the number of manufacturing steps is decreased so that mass production and growth in size of thin film transistor devices are facilitated through a printing technique. In this method, electrodes forming n-type and p-type TFT and an organic semiconductor are made of the same material in both types of TFT by the solution-process and/or printable process method. A first polarizable thin-film 7 is formed on an interface between a gate insulator and a semiconductor, and also a second polarizable thin film 8 provided on an interface between source and drain electrodes 5 and a semiconductor film 9.
    Type: Application
    Filed: June 10, 2008
    Publication date: January 1, 2009
    Inventors: Takeo Shiba, Tomihiro Hashizume, Yuji Suwa, Tadashi Arai
  • Publication number: 20080315191
    Abstract: An n-type TFT and a p-type TFT are realized by selectively changing only a cover coat without changing a TFT material using an equation for applying the magnitude of a difference in the Fermi energy between an interface of semiconductor and an electrode and between an interface of semiconductor and insulator. At this time, in order to configure a predetermined circuit, the process is performed, as a source electrode and a drain electrode of the p-type TFT and a source electrode and a drain electrode of the n-type TFT being connected all, respectively, and an unnecessary interconnection is cut by irradiating light using a scanning laser exposure apparatus or the like.
    Type: Application
    Filed: May 29, 2008
    Publication date: December 25, 2008
    Inventors: Tomihiro Hashizume, Yuji Suwa, Masaaki Fujimori, Tadashi Arai, Takeo Shiba
  • Publication number: 20080087883
    Abstract: Disclosed are a method for inexpensively reducing the contact resistance between an electrode and an organic semiconductor upon a p-type operation of the organic semiconductor; and a method for inexpensively operating, as an n-type semiconductor, an organic semiconductor that is likely to work as a p-type semiconductor. In addition, also disclosed are a p-cannel FET, an n-channel FET, and a C-TFT which can be fabricated inexpensively. Specifically, a p-type region and an n-type region is inexpensively prepared on one substrate by arranging an organic semiconductor that is likely to work as a p-type semiconductor in a p-channel FET region and an n-channel FET region of a C-TFT; and arranging a self-assembled monolayer between an electrode and the organic semiconductor in the n-channel FET region, which self-assembled monolayer is capable of allowing the organic semiconductor to work as an n-type semiconductor.
    Type: Application
    Filed: October 2, 2007
    Publication date: April 17, 2008
    Inventors: YUJI SUWA, Tomihiro Hashizume, Masahiko Ando, Takeo Shiba
  • Publication number: 20080012009
    Abstract: A method for determining the combination of the electrode and organic semiconductor with improved electron injection efficiency and hole injection efficiency in an organic TFT is provided, two types of FETS, that is, an n channel FET and a p channel FET are realized, and further, a complementary TFT (CTFT) is provided. The method for obtaining the vacuum level shift at the electrode metal/organic semiconductor interface from physical constants of constituent elements of the electrode and the organic semiconductor is provided. By changing the electrode metal through an electrochemical method, the electrodes whose electron injection and hole injection can be controlled are formed. By using these electrodes, two types of FETs such as an n channel FET and a p channel FET are realized, thereby providing a complementary TFT (CTFT).
    Type: Application
    Filed: March 14, 2007
    Publication date: January 17, 2008
    Inventors: Tomihiro Hashizume, Masaaki Fujimori, Yuji Suwa, Tadashi Arai
  • Publication number: 20070275500
    Abstract: If an organic transistor is formed by printing with a low cost, there are problems in that an inexpensive electrode material has a high contact resistance with a semiconductor, and an expensive electrode material has a low contact resistance. To solve the problems, the present invention provides an organic transistor and a method of forming the same, the organic transistor being formed with a low material cost and low manufacturing cost and providing a low contact resistance with a semiconductor and high performance. The organic transistor has electrodes whose bodies are formed mainly of an inexpensive first metal and whose surfaces are formed of a second metal that is expensive but provides high performance properties. To obtain stability of this structure with a low cost, the present invention uses a property of the second metal, in which the second metal is easily segregated on the surface of the first metal in an alloy of the first metal and the second metal.
    Type: Application
    Filed: March 19, 2007
    Publication date: November 29, 2007
    Inventors: Yuji Suwa, Tomihiro Hashizume, Masaaki Fujimori
  • Publication number: 20070185699
    Abstract: An IBIS correction tool which can be used assembled in a waveform simulation device and corrects IBIS data for a certain specific power supply voltage V0 to IBIS data for a desired power supply voltage V1 with a higher precision than the past, that is, an IBIS correction tool configured so as to read IBIS data for a power supply voltage V0 as numerical data of x-y coordinates at a data input unit, find a relative ratio (correction coefficient) between this numerical data and numerical data for a power supply voltage V1 on its x-y coordinates at a correction coefficient calculating unit, and obtain corrected IBIS data corrected for the power supply voltage V1 according to that correction coefficient at a corrected IBIS data generating unit.
    Type: Application
    Filed: October 20, 2006
    Publication date: August 9, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Yuji Suwa, Jiro Yoneda
  • Patent number: 7253023
    Abstract: An inexpensive multilayer wiring circuit board capable of conducting high frequency switching operation on the circuit while the generation of high frequency noise is being suppressed by reducing the inductance of the circuit in provided. A multilayer wiring circuit board comprising: an uppermost layer designated as a first layer on which parts are mounted; a second layer on which one of a ground layer and an electric power source layer is arranged; a third layer on which the other is arranged; and an insulating layer arranged between the ground layer and the electric power source layer. A resin layer having a thermoplastic adhesion property on both faces is used as material of the insulating layer arranged between the electric power source layer and the ground layer.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: August 7, 2007
    Assignee: Fujitsu Limited
    Inventors: Toshihiro Kusagaya, Yasuhiro Yoneda, Daisuke Mizutani, Kazuhiko Iijima, Yuji Suwa
  • Patent number: 6915249
    Abstract: In order to achieve augmentation of the accuracy in calculation of noise and augmentation of the accuracy in a noise check which is performed, for example, when an electronic circuit is designed and further realize significant reduction of the time required for a noise check and augmentation of the operation efficiency by reduction of the man-hours of a designer in a noise analysis, a noise checking apparatus includes a model production section (3) for producing a simulation model of a circuit portion relating to a noticed wiring line, a simulation section (4) for performing a simulation using the simulation model to calculate a signal waveform which propagates in the noticed wiring line and calculate a noise waveform superposed on the signal waveform for each kind of noise, a noise waveform synthesis section (5) for synthesizing the signal waveform and the noise waveforms with generation timings of the noise waveforms taken into consideration to obtain a noise composite waveform, and a noise checking section
    Type: Grant
    Filed: November 9, 2000
    Date of Patent: July 5, 2005
    Assignee: Fujitsu Limited
    Inventors: Toshiro Sato, Yuji Suwa, Yoshiyuki Iwakura, Kazunari Gotou, Toshiaki Sato, Kazuyoshi Kanei, Masaki Tosaka, Yasuhiro Yamashita
  • Publication number: 20050098882
    Abstract: An inexpensive multilayer wiring circuit board capable of conducting high frequency switching operation on the circuit while the generation of high frequency noise is being suppressed by reducing the inductance of the circuit in provided. A multilayer wiring circuit board comprising: an uppermost layer designated as a first layer on which parts are mounted; a second layer on which one of a ground layer and an electric power source layer is arranged; a third layer on which the other is arranged; and an insulating layer arranged between the ground layer and the electric power source layer. A resin layer having a thermoplastic adhesion property on both faces is used as material of the insulating layer arranged between the electric power source layer and the ground layer.
    Type: Application
    Filed: December 22, 2004
    Publication date: May 12, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Toshihiro Kusagaya, Yasuhiro Yoneda, Daisuke Mizutani, Kazuhiko Iijima, Yuji Suwa
  • Patent number: 6780698
    Abstract: A method for producing a semiconductor device which comprises causing a dopant present in a semiconductor substrate to segregate in the surface of said semiconductor substrate, thereby forming a thin layer which has a higher dopant concentration than said substrate. The thin layer formed by segregation prevents punch-through which occurs as the result of miniaturization of MOSFET. This method permits economical delta doping without sacrificing the device characteristics.
    Type: Grant
    Filed: July 15, 2002
    Date of Patent: August 24, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yuji Suwa, Tomihiro Hashizume, Ken Yamaguchi, Masaaki Fujimori
  • Publication number: 20030119247
    Abstract: A method for producing a semiconductor device which comprises causing a dopant present in a semiconductor substrate to segregate in the surface of said semiconductor substrate, thereby forming a thin layer which has a higher dopant concentration than said substrate. The thin layer formed by segregation prevents punch-through which occurs as the result of miniaturization of MOSFET. This method permits economical delta doping without sacrificing the device characteristics.
    Type: Application
    Filed: July 15, 2002
    Publication date: June 26, 2003
    Inventors: Yuji Suwa, Tomihiro Hashizume, Ken Yamaguchi, Masaaki Fujimori
  • Publication number: 20030063453
    Abstract: An inexpensive multilayer wiring circuit board capable of conducting high frequency switching operation on the circuit while the generation of high frequency noise is being suppressed by reducing the inductance of the circuit in provided. A multilayer wiring circuit board comprising: an uppermost layer designated as a first layer on which parts are mounted; a second layer on which one of a ground layer and an electric power source layer is arranged; a third layer on which the other is arranged; and an insulating layer arranged between the ground layer and the electric power source layer. A resin layer having a thermoplastic adhesion property on both faces is used as material of the insulating layer arranged between the electric power source layer and the ground layer.
    Type: Application
    Filed: September 26, 2002
    Publication date: April 3, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Toshihiro Kusagaya, Yasuhiro Yoneda, Daisuke Mizutani, Kazuhiko Iijima, Yuji Suwa
  • Patent number: 6475650
    Abstract: A ferromagnetic material can be formed in a very small size on the order of an atomic size and is capable of being stably magnetized. The ferromagnetic material comprises basic unit structures each consisting of a first atom (11), a second atom (12) of the same kind as the first atom (11), and a third atom (or atomic group) (13) of the same kind as the first atom (11) or of a kind different from that of the first atom (11). In each of the basic unit structures, the atoms are arranged on a surface of a substrate so that a chemical bond (14) is formed between the first atom or molecule and the third atom or molecule, a chemical bond (14) is formed between the second atom or molecule and the third atom or molecule, and a chemical bond or an electron path (15) not passing the third atom is formed between the first and the second atom or molecule, wherein said third atoms or molecules consist of As atoms.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: November 5, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Satoshi Watanabe, Toshiyuki Onogi, Masahiko Ichimura, Yoshimasa Ono, Tomihiro Hashizume, Yasuo Wada, Yuji Suwa
  • Publication number: 20020012813
    Abstract: A ferromagnetic material can be formed in a very small size on the order of an atomic size and is capable of being stably magnetized. The ferromagnetic material comprises basic unit structures each consisting of a first atom (11), a second atom (12) of the same kind as the first atom (11), and a third atom (or atomic group) (13) of the same kind as the first atom (11) or of a kind different from that of the first atom (11). In each of the basic unit structures, the atoms are arranged on a surface of a substrate so that a chemical bond (14) is formed between the first atom or molecule and the third atom or molecule, a chemical bond (14) is formed between the second atom or molecule and the third atom or molecule, and a chemical bond or an electron path (15) not passing the third atom is formed between the first and the second atom or molecule, wherein said third atoms or molecules consist of As atoms.
    Type: Application
    Filed: September 25, 2001
    Publication date: January 31, 2002
    Inventors: Satoshi Watanabe, Toshiyuki Onogi, Masahiko Ichimura, Yoshimasa Ono, Tomihiro Hashizume, Yasuo Wada, Yuji Suwa
  • Patent number: 6299990
    Abstract: A ferromagnetic material can be formed in a very small size on the order of an atomic size and is capable of being stably magnetized. The ferromagnetic material comprises basic unit structures each consisting of a first atom (11), a second atom (12) of the same kind as the first atom (11), and a third atom (or atomic group) (13) of the same kind as the first atom (11) or of a kind different from that of the first atom (11). In each of the basic unit structures, the atoms are arranged on a surface of a substrate so that a chemical bond (14) is formed between the first atom or molecule and the third atom or molecule, a chemical bond (14) is formed between the second atom or molecule and the third atom or molecule, and a chemical bond or an electron path (15) not passing the third atom is formed between the first and the second atom or molecule, wherein said third atoms or molecules consist of As atoms.
    Type: Grant
    Filed: August 17, 1999
    Date of Patent: October 9, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Satoshi Watanabe, Toshiyuki Onogi, Masahiko Ichimura, Yoshimasa Ono, Tomihiro Hashizume, Yasuo Wada, Yuji Suwa
  • Patent number: 5389968
    Abstract: A CCD television camera has a head part separated from the rest of the camera. The camera head part contains a CCD imaging device and is connected by only a single line coaxial cable to a main part containing a DC power source, a line flag output circuit, and a one H-alternate switch. The coaxial cable may be up to several hundred meters in length. Respective ends of the coaxial cable are connected to the head and main parts through hydrid coils to facilitate sending of DC power current and an accurately controlled sinusoidal clock frequency signal from the main part to the camera head part, and the sending of video signals over the same single cable line from the camera head part to the main part. The hybrid coils are tuned for resonance with the clock frequency and a PLL circuit, including the coaxial cable, regulates the clock frequency to adjust for different lengths of cable.
    Type: Grant
    Filed: April 3, 1992
    Date of Patent: February 14, 1995
    Assignees: Yugengaisha Wai-Kei Kikaku, Komatsu Denshi Kabushiki Kaisha
    Inventors: Yukio Koyanagi, Yuji Suwa