Patents by Inventor Yuji Tsushima

Yuji Tsushima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8214559
    Abstract: Arbitration of IO accesses and band control based on the priority of virtual servers is enabled while curbing performance overhead during IO sharing among the virtual servers. A virtual machine system includes a CPU, a memory, a hypervisor that generates plural virtual servers, and an IO controller that controls an IO interface. The IO controller includes: a DMA receiving unit that receives DMA requests from the IO interface; a decoder that decodes received DMA requests and locates the corresponding virtual servers; a DMA monitoring counter that monitors DMA processing status for each of the virtual servers; a threshold register set in advance for each of the virtual servers; and a priority deciding unit that compares the DMA monitoring counter and the value of the threshold register, and based on processing priority obtained as a result of the comparison, decides the priority of processing of the received DMA requests.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: July 3, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Toshiomi Moriki, Keitaro Uehara, Yuji Tsushima
  • Publication number: 20120124575
    Abstract: The program attains compatibility of suppression of an overhead accompanying page exception handling in the case of operating a program whose amount of memory use is large on a virtual machine and suppression of the overhead accompanying page exception handling in the case of operating a first OS that has a function of making another OS run on a virtual machine. A VMM creates a shadow PT (Page Table) for prohibiting reading-writing of privileged memory that requires emulation of reading/writing by using a RSV-bit, and registers the shadow PT and the second PT that a second OS operating on the first OS has in an x86 compatible CPU equipped with page exception detecting function using two PT's. When a page exception occurs, the VMM refers to cause code of the page exception and, when a P field of the cause code is 0, determines immediately that emulation is unnecessary.
    Type: Application
    Filed: December 28, 2011
    Publication date: May 17, 2012
    Applicant: HITACHI, LTD.
    Inventors: Naoya HATTORI, Toshiomi MORIKI, Yuji TSUSHIMA
  • Publication number: 20120030427
    Abstract: Disclosed is a computer system that includes a first apparatus, which stores data and metadata in a storage, and multiple units of a second apparatus, which store a copy of data and metadata in the first apparatus in a cache. The first apparatus acquires throughput achieved when the units of the second apparatus access the data in the storage as first access information, acquires throughput achieved when the units of the second apparatus access data thereof as second access information, and selects either a first judgment mode or a second judgment mode in accordance with the first access information and the second access information. This reduces the amount of network traffic for metadata acquisition, thereby increasing the speed of data access.
    Type: Application
    Filed: July 11, 2011
    Publication date: February 2, 2012
    Applicant: Hitachi, Ltd.
    Inventors: Hitoshi HAYAKAWA, Daisuke Ito, Yuji Tsushima
  • Patent number: 8104035
    Abstract: Provided is the virtual computer system including an emulation module for emulating an operation based on an operation code for executing the operation of hardware of a server system, an exception event handler module for calling the emulation module when an exception event is generated by a CPU, a code management module for managing a promotion code for emulating the operation of the hardware of the server system, a frequency judgment module for judging whether a frequency of the operation of the hardware of the server system is high, and a switching module for determining whether to call the emulation module by the exception event handler module or to call the emulation module by executing the promotion code based on the judged frequency. Accordingly, the virtual computer system can simultaneously achieve high performance and memory saving in an emulation system.
    Type: Grant
    Filed: February 8, 2007
    Date of Patent: January 24, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Naoya Hattori, Toshiomi Moriki, Yuji Tsushima
  • Patent number: 8099575
    Abstract: The program attains compatibility of suppression of an overhead accompanying page exception handling in the case of operating a program whose amount of memory use is large on a virtual machine and suppression of the overhead accompanying page exception handling in the case of operating a first OS that has a function of making another OS run on a virtual machine. A VMM creates a shadow PT (Page Table) for prohibiting reading-writing of privileged memory that requires emulation of reading/writing by using a RSV-bit, and registers the shadow PT and the second PT that a second OS operating on the first OS has in an x86 compatible CPU equipped with a page exception detecting function using two PT's. When a page exception occurs, the VMM refers to a cause code of the page exception and, when a P field of the cause code is 0, determines immediately that emulation is unnecessary.
    Type: Grant
    Filed: February 13, 2008
    Date of Patent: January 17, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Naoya Hattori, Toshiomi Moriki, Yuji Tsushima
  • Patent number: 8086823
    Abstract: A method is provided which eliminates redundancy from the shadow PT operation performed by the virtual machine monitor (VMM) when the guest operating system running on a virtual machine updates a guest page table (PT) address. The VMM associates a plurality of shadow PTs with guest PTs and allocates their relation in memory. When it detects the update of a guest PT address, the VMM searches for a shadow PT corresponding to the updated guest PT. If the associated shadow PT exists, the VMM omits rewriting the shadow PT and registers the address of the shadow PT with the central processing unit (CPU). If the associated shadow PT does not exist, the VMM allocates a memory, creates a shadow PT, registers an address of the created shadow PT with the CPU, and records a relationship between the updated guest PT and the generated shadow PT.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: December 27, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Naoya Hattori, Toshiomi Moriki, Yuji Tsushima
  • Patent number: 8078764
    Abstract: The physical server includes a hypervisor for managing an association between the virtual server and the I/O device allocated to the virtual server. The I/O switch includes: a setting register for retaining a request to inhibit a transaction from being issued from the I/O device to the virtual server; a Tx inhibition control module for performing an inhibition of the transaction from the I/O device to the virtual server, and guaranteeing a completion of a transaction from the I/O device issued before the inhibition; a virtualization assist module for converting an address of the virtual server into an address within a memory of the physical server; and a switch management module for managing a configuration of the I/O switch.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: December 13, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Jun Okitsu, Yoshiko Yasuda, Takashige Baba, Keitaro Uehara, Yuji Tsushima
  • Publication number: 20110289502
    Abstract: Arbitration of IO accesses and band control based on the priority of virtual servers is enabled while curbing performance overhead during IO sharing among the virtual servers. A virtual machine system includes a CPU, a memory, a hypervisor that generates plural virtual servers, and an IO controller that controls an IO interface. The IO controller includes: a DMA receiving unit that receives DMA requests from the IO interface; a decoder that decodes received DMA requests and locates the corresponding virtual servers; a DMA monitoring counter that monitors DMA processing status for each of the virtual servers; a threshold register set in advance for each of the virtual servers; and a priority deciding unit that compares the DMA monitoring counter and the value of the threshold register, and based on processing priority obtained as a result of the comparison, decides the priority of processing of the received DMA requests.
    Type: Application
    Filed: August 4, 2011
    Publication date: November 24, 2011
    Applicant: HITACHI, LTD.
    Inventors: Toshiomi Moriki, Keitaro Uehara, Yuji Tsushima
  • Patent number: 8046520
    Abstract: A resource management module of a management server for controlling a multi-root I/O manager connected to a PCI switch for connecting a plurality of I/O devices and a plurality of computers with each other includes: failure handling content information indicating, for each computer sharing a multi-root I/O device, a content of a failure handling at an occurrence of a failure in the multi-root I/O device; and failure handling availability status information indicating whether a hardware reset of the multi-root I/O device is possible and updates, upon reception of a notification of the occurrence of the failure in the multi-root I/O device, the failure handling availability status information, and instructs, based on the failure handling availability status information, the multi-root I/O manager to restrain or cancel the hardware reset of the multi-root I/O device.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: October 25, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Takashige Baba, Keitaro Uehara, Yuji Tsushima
  • Publication number: 20110225373
    Abstract: A computer system including: a file server, cache servers, and a cache management server, wherein: the cache server obtains the authority information from the cache management server, in a case of receiving a command to process a file, wherein the cache server refers to the obtained authority information, wherein the cache server executes the command to process the file, in a case where the cache server has an administration right of the cache data of the file, wherein the cache management server sends to the cache server an update command for transferring the administration right of the cache data to the other cache server, wherein the cache server sends the update command to the other cache server after receiving the update command, and executes a update procedure in which a lock management information is updated.
    Type: Application
    Filed: November 16, 2010
    Publication date: September 15, 2011
    Inventors: Daisuke ITO, Yuji Tsushima, Hitoshi Hayakawa
  • Patent number: 8015431
    Abstract: Provided is a failover method for a cluster system for realizing smooth failover of the guest OS's, even when there are many guest OS's, while reducing consumption of computer resources of a server. Smooth failover is realized by preventing competition during failover even when the number of guest OS's is increased. In a cluster configuration in which a slave/master cluster program is operated in a guest OS/host OS, the master cluster program (510) collects and transmits heartbeats of the slave cluster program, thereby realizing failure monitoring through the certain amount of heartbeats without depending on the number of guest OS's. Further, when the master cluster program monitors failures of the slave cluster program of its own computer to find a normal operation of the guest OS, the amount of communication through heartbeats is reduced by eliminating the necessity of communication to a standby system slave cluster program.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: September 6, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Tsunehiko Baba, Yuji Tsushima, Toshiomi Moriki
  • Patent number: 8010719
    Abstract: Arbitration of IO accesses and band control based on the priority of virtual servers is enabled while curbing performance overhead during IO sharing among the virtual servers. A virtual machine system includes a CPU, a memory, a hypervisor that generates plural virtual servers, and an IO controller that controls an IO interface. The IO controller includes: a DMA receiving unit that receives DMA requests from the IO interface; a decoder that decodes received DMA requests and locates the corresponding virtual servers; a DMA monitoring counter that monitors DMA processing status for each of the virtual servers; a threshold register set in advance for each of the virtual servers; and a priority deciding unit that compares the DMA monitoring counter and the value of the threshold register, and based on processing priority obtained as a result of the comparison, decides the priority of processing of the received DMA requests.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: August 30, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Toshiomi Moriki, Keitaro Uehara, Yuji Tsushima
  • Publication number: 20110202658
    Abstract: A system permitting alteration of the information processing position, where an existing information system is used, while minimizing alterations in configuration or the like, is to be provided. Intelligent nodes each having an information processing section and any desired address altering section are arranged on boundaries of a network where packets are likely to pass. This node has a flow table for recognizing as a flow a group of packets transmitted from each user's terminal, a flow status table for determining the connection state and the next destination address or the final destination address of each flow, and a module to observe the loaded state of its own information processing function. It rewrites the destination address of any flow not in a connection-established state in the flow status table to a less loaded one out of its own information processing function section or external information processing apparatus.
    Type: Application
    Filed: February 16, 2011
    Publication date: August 18, 2011
    Inventors: Michitaka OKUNO, Takeki Yazaki, Yuji Tsushima, Hidetaka Aoki
  • Patent number: 7992032
    Abstract: Even when a large number of guest OSs exist, a failover method meeting high availability needed by the guest OSs is provided for the each guest OS. In the event of a physical or logical change of a system, or change of operation states, a smooth failover method can be realized by preventing the consumption of resource amounts due to excessive failover methods, and the occurrence of systemdown due to an inadequate failover method. In a server virtualization environment, in a cluster configuration having a failover method due to hot standby and cold standby, by selecting a failover method meeting high availability requirements specifying performance during failover of applications on the guest OSs, a suitable cluster configuration is realized. Failure monitoring is realized by quantitative heartbeat.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: August 2, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Tsunehiko Baba, Toshiomi Moriki, Yuji Tsushima
  • Patent number: 7975076
    Abstract: When a subject of access of a transaction from an IO device is not any resource allocated to a logical partition to which the device having issued the transaction belongs, a report as an error is sent to a CPU, while the transaction is finished on the IO bus. To prevent a transaction between IO devices from gaining access to any resource in another logical partition, one access permission bit is provided for each combination of all the IO devices, and the access is permitted only when the bit has a predetermined value. A reset signal is provided by IO slot so that only an IO slot allocated to a specific logical partition can be reset without affecting any other logical partition. A transaction issued from an IO device in one logical partition is prevented from gaining access to a resource in another logical partition, while proper error handling can be performed.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: July 5, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Toshiomi Moriki, Keitaro Uehara, Yuji Tsushima
  • Patent number: 7925817
    Abstract: A computer system includes I/O devices coupled to PCI switches coupled via interfaces of a plurality of servers, and a management block for managing configurations of the PCI switches. The management block is configured to: set, to the PCI switch, a first access path including a virtual bridge coupling the interface of an active server and a virtual switch, and a virtual bridge coupling the I/O device and the virtual switch; set, to the PCI switch, a second access path including a virtual bridge coupling the interface of standby server of the plurality of servers and a virtual switch, and a virtual bridge coupling the I/O device used by the active server and the virtual switch; disable mapping of the second access path between the I/O device and the virtual bridge; and instruct the standby server to make access to the I/O device.
    Type: Grant
    Filed: April 13, 2009
    Date of Patent: April 12, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Keitaro Uehara, Yuji Tsushima, Takashige Baba
  • Patent number: 7890669
    Abstract: Provided is a computer system in which an I/O card is shared among physical servers and logical servers. Servers are set in advance such that one I/O card is used exclusively by one physical or logical server, or shared among a plurality of servers. An I/O hub allocates a virtual MM I/O address unique to each physical or logical server to a physical MM I/O address associated with each I/O card. The I/O hub keeps allocation information indicating the relation between the allocated virtual MM I/O address, the physical MM I/O address, and a server identifier unique to each physical or logical server. When a request to access an I/O card is sent from a physical or logical server, the allocation information is referred to and a server identifier is extracted from the access request. The extracted server identifier is used to identify the physical or logical server that has made the access request.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: February 15, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Keitaro Uehara, Yuji Tsushima, Toshiomi Moriki, Yoshiko Yasuda
  • Publication number: 20110004706
    Abstract: When a subject of access of a transaction from an IO device is not any resource allocated to a logical partition to which the device having issued the transaction belongs, a report as an error is sent to a CPU, while the transaction is finished on the IO bus. To prevent a transaction between IO devices from gaining access to any resource in another logical partition, one access permission bit is provided for each combination of all the IO devices, and the access is permitted only when the bit has a predetermined value. A reset signal is provided by IO slot so that only an IO slot allocated to a specific logical partition can be reset without affecting any other logical partition. A transaction issued from an IO device in one logical partition is prevented from gaining access to a resource in another logical partition, while proper error handling can be performed.
    Type: Application
    Filed: September 8, 2010
    Publication date: January 6, 2011
    Inventors: Toshiomi Moriki, Keitaro Uehara, Yuji Tsushima
  • Publication number: 20100332722
    Abstract: In a two-level virtual machine system having child VMMs operating on a parent VMM, the field update frequency of VMCS and VMCB which control a VMM assist function of a CPU is not uniform. A G field requiring reflection of emulation results is higher in update frequency than a C field. The semiconductor quantity and power dissipation caused by the assist function expansion tend to increase in the C field used for a condition decision as compared with the G field simply retaining a value because influence upon the CPU operation is greater in the C field. Therefore, events relating to the G field which is high in update frequency and less in increase of semiconductor quantity and power dissipation caused by the assist function expansion are coped with by the CPU with its assist function expanded. Events relating to the C field are coped with by the parent VMM.
    Type: Application
    Filed: June 21, 2010
    Publication date: December 30, 2010
    Applicant: HITACHI, LTD.
    Inventors: Eiichiro OIWA, Naoya HATTORI, Toshiomi MORIKI, Yuji TSUSHIMA
  • Publication number: 20100312943
    Abstract: It is provided a computer system comprising a plurality of computers; a PCI switch; and a plurality of I/O devices connected to the PCI switch, wherein the communication path includes a virtual switch and virtual bridges, and the PCI switch comprises a communication path generating module for setting the virtual switches and the virtual bridges, a virtual switch group management module for creating a virtual switch group including the at least one of the virtual switches, and setting an enabled flag to one of the virtual switches included in the virtual switch group, and a port management module for managing relation between each of the generated communication paths and the plurality of ports included in the each of the generated communication paths.
    Type: Application
    Filed: May 28, 2010
    Publication date: December 9, 2010
    Applicant: HITACHI, LTD.
    Inventors: Keitaro UEHARA, Takashige BABA, Yuji TSUSHIMA