Patents by Inventor Yuji Tsushima

Yuji Tsushima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100262741
    Abstract: A method for making it possible for a virtualization software (VMM) to generally identify a PCI function of an interrupt requester presupposing the existing I/O devices based on the PCI express is provided. An interrupt relay circuit is provided between an I/O device based on the PCI express and a PCI express bridge. The interrupt relay circuit receives and relays an interrupt transaction issued by the I/O device, and records whether there is an interrupt request in an interrupt indicator in association with an interrupt identifier. A VMM 114 uniquely identifies an I/O device of interrupt requester by referring to the interrupt indicator 134.
    Type: Application
    Filed: April 12, 2010
    Publication date: October 14, 2010
    Inventors: Norimitsu HAYAKAWA, Toshiomi Moriki, Yuji Tsushima, Naoya Hattori
  • Patent number: 7797466
    Abstract: When a subject of access of a transaction from an IO device is not any resource allocated to a logical partition to which the device having issued the transaction belongs, a report as an error is sent to a CPU, while the transaction is finished on the IO bus. To prevent a transaction between IO devices from gaining access to any resource in another logical partition, one access permission bit is provided for each combination of all the IO devices, and the access is permitted only when the bit has a predetermined value. A reset signal is provided by IO slot so that only an IO slot allocated to a specific logical partition can be reset without affecting any other logical partition. A transaction issued from an IO device in one logical partition is prevented from gaining access to a resource in another logical partition, while proper error handling can be performed.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: September 14, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Toshiomi Moriki, Keitaro Uehara, Yuji Tsushima
  • Publication number: 20100211717
    Abstract: It is provided a computer system including computers, PCI switches each having first and second ports, a switch management module and a power control module. The switch management module includes an identifying module for identifying a first port coupled to the computer to be booted up, and notifying the PCI switch of the first port, an instruction module for instructing the power control module to boot up the computer, and an allocation management module for managing allocation of one of the I/O device to the computer and notifying the one of the PCI switches of the allocation after the computer is booted up. The PCI switches includes a preventing control module for preventing the computer from detecting a configuration of the first port, and a virtual switch generating module for generating a virtual switch that couples the first port and the second port based on the notification.
    Type: Application
    Filed: February 19, 2010
    Publication date: August 19, 2010
    Inventors: Keitaro Uehara, Takashige Baba, Yuji Tsushima
  • Publication number: 20100205347
    Abstract: A method is provided which eliminates redundancy from the shadow PT operation performed by the virtual machine monitor (VMM) when the guest operating system running on a virtual machine updates a guest page table (PT) address. The VMM associates a plurality of shadow PTs with guest PTs and allocates their relation in memory. When it detects the update of a guest PT address, the VMM searches for a shadow PT corresponding to the updated guest PT. If the associated shadow PT exists, the VMM omits rewriting the shadow PT and registers the address of the shadow PT with the central processing unit (CPU). If the associated shadow PT does not exist, the VMM allocates a memory, creates a shadow PT, registers an address of the created shadow PT with the CPU, and records a relationship between the updated guest PT and the generated shadow PT.
    Type: Application
    Filed: April 23, 2010
    Publication date: August 12, 2010
    Inventors: Naoya Hattori, Toshiomi Moriki, Yuji Tsushima
  • Patent number: 7769031
    Abstract: A plurality of machine systems constituted by different VLAN constitution methods are integrated on one machine system by using virtual machines. An operation can be switched for virtual network interface cards to VLAN communication corresponding to VLAN ID set to a virtual network interface card or to VLAN communication corresponding to VLAN ID set by OS on a virtual machine using the virtual network interface card depending on whether or not VLAN ID is set.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: August 3, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Mitome, Yuji Tsushima
  • Publication number: 20100153615
    Abstract: A resource management module of a management server for controlling a multi-root I/O manager connected to a PCI switch for connecting a plurality of I/O devices and a plurality of computers with each other includes: failure handling content information indicating, for each computer sharing a multi-root I/O device, a content of a failure handling at an occurrence of a failure in the multi-root I/O device; and failure handling availability status information indicating whether a hardware reset of the multi-root I/O device is possible and updates, upon reception of a notification of the occurrence of the failure in the multi-root I/O device, the failure handling availability status information, and instructs, based on the failure handling availability status information, the multi-root I/O manager to restrain or cancel the hardware reset of the multi-root I/O device.
    Type: Application
    Filed: December 11, 2009
    Publication date: June 17, 2010
    Applicant: HITACHI, LTD.
    Inventors: Takashige BABA, Keitaro UEHARA, Yuji TSUSHIMA
  • Patent number: 7734893
    Abstract: A method is provided which eliminates redundancy from the shadow PT operation performed by the virtual machine monitor (VMM) when the guest operating system running on a virtual machine updates a guest page table (PT) address. The VMM associates a plurality of shadow PTs with guest PTs and allocates their relation in memory. When it detects the update of a guest PT address, the VMM searches for a shadow PT corresponding to the updated guest PT. If the associated shadow PT exists, the VMM omits rewriting the shadow PT and registers the address of the shadow PT with the central processing unit (CPU). If the associated shadow PT does not exist, the VMM allocates a memory, creates a shadow PT, registers an address of the created shadow PT with the CPU, and records a relationship between the updated guest PT and the generated shadow PT.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: June 8, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Naoya Hattori, Toshiomi Moriki, Yuji Tsushima
  • Publication number: 20100138208
    Abstract: A VMM disables an interrupt interception flag on at least one CPU to execute, upon reception of an interrupt, an interrupt handler code of an OS, and enables the interrupt interception flag on the at least one CPU to execute, upon the reception of the interrupt, an emulator in the VMM. When, to a virtual machine, an I/O device is assigned in a dedicated form, and when the CPU is assigned while the interrupt interception is disabled, a destination of the interrupt from the physical I/O device is set to the corresponding CPU on which the interrupt interception is disabled. When, to the virtual machine, the I/O device is assigned in a shared form, or when the CPU is assigned while the interrupt interception is disabled, the destination of the interrupt from the physical I/O device is set to the corresponding CPU on which the interrupt interception is enabled.
    Type: Application
    Filed: November 24, 2009
    Publication date: June 3, 2010
    Inventors: Naoya HATTORI, Toshiomi Moriki, Takashige Baba, Yuji Tsushima
  • Patent number: 7725642
    Abstract: This invention provides a program product for a virtual computer that partitions a physical computer into a plurality of logical partitions through a hypervisor and runs an OS on each of the logical partitions, the program product including: a procedure (S1) of detecting an exception or an interruption occurring in the physical computer; a procedure (S2) of identifying an OS on a logical partition where the detected exception or interruption occurring; a procedure (S4) of copying a given storage area that contains an instruction that is the subject of the exception or interruption from a storage area where the identified OS is stored to a storage area that is managed by the hypervisor; a procedure (S6) of replacing, in the copied storage area, the exception or interruption subject instruction with an instruction that substitutes for the exception or interruption subject instruction; and a procedure (S7) of moving a location where the physical computer executes an instruction to the copied storage area.
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: May 25, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Yuji Tsushima, Toshiomi Moriki, Naoya Hattori
  • Patent number: 7725632
    Abstract: Disclosed herewith is a composite type computer system that can assure that a PCI tree to be allocated to a computer is configured completely before the computer is powered. The composite type computer system includes a PCI switch that connects plural computers through PCI interfaces; plural PCI devices connected to the PCI switch; a system controller that controls the computers; and a PCI manager that controls allocation of the PCI devices to the computers.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: May 25, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Takashige Baba, Jun Okitsu, Yuji Tsushima, Nobuyuki Muranaka, Keitaro Uehara
  • Publication number: 20100115513
    Abstract: Provided is a virtual machine including a first virtualization module operating on a physical CPU, for providing a first CPU, and a second virtualization module operating on the first CPU, for providing second CPU. The second virtualization module includes first processor control information holding a state of the first CPU obtained at a time of execution of the user program. The first virtualization module includes second processor control information containing a state of the physical CPU obtained at the time of the execution of the second virtualization module, third processor control information containing a state of the physical CPU obtained at the time of the execution of the user program, and prefetch entry information in which information to be prefetched from the third processor control information is set, and, upon detection of a event, the information set in the prefetch entry information is reflected to the first processor control information.
    Type: Application
    Filed: October 30, 2009
    Publication date: May 6, 2010
    Inventors: Toshiomi MORIKI, Naoya Hattori, Yuji Tsushima
  • Publication number: 20100017643
    Abstract: Provided is a failover method for a cluster system for realizing smooth failover of the guest OS's, even when there are many guest OS's, while reducing consumption of computer resources of a server. Smooth failover is realized by preventing competition during failover even when the number of guest OS's is increased. In a cluster configuration in which a slave/master cluster program is operated in a guest OS/host OS, the master cluster program (510) collects and transmits heartbeats of the slave cluster program, thereby realizing failure monitoring through the certain amount of heartbeats without depending on the number of guest OS's. Further, when the master cluster program monitors failures of the slave cluster program of its own computer to find a normal operation of the guest OS, the amount of communication through heartbeats is reduced by eliminating the necessity of communication to a standby system slave cluster program.
    Type: Application
    Filed: September 23, 2009
    Publication date: January 21, 2010
    Inventors: Tsunehiko Baba, Yuji Tsushima, Toshiomi Moriki
  • Patent number: 7617411
    Abstract: Provided is a failover method for a cluster system for realizing smooth failover of the guest OS's, even when there are many guest OS's, while reducing consumption of computer resources of a server. Smooth failover is realized by preventing competition during failover even when the number of guest OS's is increased. In a cluster configuration in which a slave/master cluster program is operated in a guest OS/host OS, the master cluster program (510) collects and transmits heartbeats of the slave cluster program, thereby realizing failure monitoring through the certain amount of heartbeats without depending on the number of guest OS's. Further, when the master cluster program monitors failures of the slave cluster program of its own computer to find a normal operation of the guest OS, the amount of communication through heartbeats is reduced by eliminating the necessity of communication to a standby system slave cluster program.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: November 10, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Tsunehiko Baba, Yuji Tsushima, Toshiomi Moriki
  • Publication number: 20090265501
    Abstract: Provided is a computer system including I/O devices coupled to PCI switches coupled via interfaces of a plurality of servers, and a management block for managing configurations of the PCI switches. The management block is configured to: set, to the PCI switch, a first access path including a virtual bridge coupling the interface of a first server and a virtual switch, and a virtual bridge coupling the I/O device and the virtual switch; set, to the PCI switch, a second access path including a virtual bridge coupling the interface of a second server of the plurality of servers and a virtual switch, and a virtual bridge coupling the I/O device used by the first server and the virtual switch; disable mapping of the second access path between the I/O device and the virtual bridge; and instruct the second server to make access to the I/O device.
    Type: Application
    Filed: April 13, 2009
    Publication date: October 22, 2009
    Applicant: HITACHI, LTD.
    Inventors: Keitaro Uehara, Yuji Tsushima, Takashige Baba
  • Publication number: 20090216913
    Abstract: When a subject of access of a transaction from an IO device is not any resource allocated to a logical partition to which the device having issued the transaction belongs, a report as an error is sent to a CPU, while the transaction is finished on the IO bus. To prevent a transaction between IO devices from gaining access to any resource in another logical partition, one access permission bit is provided for each combination of all the IO devices, and the access is permitted only when the bit has a predetermined value. A reset signal is provided by IO slot so that only an IO slot allocated to a specific logical partition can be reset without affecting any other logical partition. A transaction issued from an IO device in one logical partition is prevented from gaining access to a resource in another logical partition, while proper error handling can be performed.
    Type: Application
    Filed: April 29, 2009
    Publication date: August 27, 2009
    Inventors: Toshiomi Moriki, Keitaro Uehara, Yuji Tsushima
  • Patent number: 7577864
    Abstract: Provided is a technology for increasing reliability of communication carried out by OSes and application programs operating on logical partitions set on a computer. The computer has multiple logical partitions constructed therein by a control program, the physical interfaces are shared by virtual interfaces respectively set for the multiple logical partitions, and the memory module stores management information indicating correspondences between the physical interface and the virtual interface.
    Type: Grant
    Filed: September 1, 2006
    Date of Patent: August 18, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhide Horimoto, Toshiomi Moriki, Yuji Tsushima, Takuichi Hoshina
  • Publication number: 20090198862
    Abstract: The physical server includes a hypervisor for managing an association between the virtual server and the I/O device allocated to the virtual server. The I/O switch includes: a setting register for retaining a request to inhibit a transaction from being issued from the I/O device to the virtual server; a Tx inhibition control module for performing an inhibition of the transaction from the I/O device to the virtual server, and guaranteeing a completion of a transaction from the I/O device issued before the inhibition; a virtualization assist module for converting an address of the virtual server into an address within a memory of the physical server; and a switch management module for managing a configuration of the I/O switch.
    Type: Application
    Filed: August 20, 2008
    Publication date: August 6, 2009
    Inventors: Jun Okitsu, Yoshiko Yasuda, Takashige Baba, Keitaro Uehara, Yuji Tsushima
  • Publication number: 20090187694
    Abstract: Disclosed herewith is a composite type computer system that can assure that a PCI tree to be allocated to a computer is configured completely before the computer is powered. The composite type computer system includes a PCI switch that connects plural computers through PCI interfaces; plural PCI devices connected to the PCI switch; a system controller that controls the computers; and a PCI manager that controls allocation of the PCI devices to the computers.
    Type: Application
    Filed: August 5, 2008
    Publication date: July 23, 2009
    Inventors: Takashige Baba, Jun Okitsu, Yuji Tsushima, Nobuyuki Muranaka, Keitaro Uehara
  • Publication number: 20090150896
    Abstract: Provided is a method of controlling a virtual computer system in which a physical computer includes a plurality of physical CPUs that is switchable between a sleep state and a normal state, and a virtualization control unit divides the physical computer into a plurality of logical partitions to run a guest OS in each of the logical partitions and controls allocation of resources of the physical computer to the logical partitions, causes the virtualization control unit to: receive an operation instruction for operating the logical partitions; and if the operation instruction is for deleting a virtual CPU from one of the logical partitions, delete this virtual CPU from a table for managing virtual CPU-physical CPU allocation and put, if the deleting leaves no virtual CPUs allocated to one of the physical CPUs that has been allocated the deleted virtual CPU, this one of the physical CPUs into the sleep state.
    Type: Application
    Filed: December 4, 2008
    Publication date: June 11, 2009
    Inventors: Yuji TSUSHIMA, Keitaro UEHARA, Toshiomi MORIKI, Naoya HATTORI
  • Publication number: 20090138887
    Abstract: In order to provide an interface of acquiring physical position information of an I/O device on a virtual machine monitor having an exclusive allocation function of the I/O device and optimize allocation of a resource to a virtual server by using the acquired physical position information, a virtual machine monitor includes an interface of allocating a resource in accordance with a given policy (a parameter of determining to which a priority is given in distributing resources) for an I/O device, a CPU NO., and a memory amount request to guest OS. Further, the virtual machine monitor includes an interface of pertinently converting physical position information of the resource allocated by the virtual machine monitor to notice to guest OS.
    Type: Application
    Filed: August 5, 2008
    Publication date: May 28, 2009
    Inventors: Keitaro Uehara, Yuji Tsushima