Abstract: A non-volatile memory includes a plurality of word lines connected to non-volatile memory cells, a plurality of driver lines configured to carry one or more word line voltages, and a plurality of word line switches that selectively connect the driver lines to the word lines. To more efficiently utilize space on the die, the word line switches are arranged in a plurality of three dimensional stacks such that each stack of the plurality of stacks comprises multiple word line switches vertically stacked.

Abstract: Fabricating a regrown GaN p-n junction includes depositing a n-GaN layer on a substrate including n+-GaN, etching a surface of the n-GaN layer to yield an etched surface, depositing a p-GaN layer on the etched surface, etching a portion of the n-GaN layer and a portion of the p-GaN layer to yield a mesa opposite the substrate, and passivating a portion of the p-GaN layer around an edge of the mesa. The regrown GaN p-n junction is defined at an interface between the n-GaN layer and the p-GaN layer. The regrown GaN p-n junction includes a substrate, a n-GaN layer on the substrate having an etched surface, a p-GaN layer on the etched surface, a mesa defined by an etched portion of the n-GaN layer and an etched portion of the p-GaN layer, and a passivated portion of the p-GaN layer around an edge of the mesa.

Abstract: Fabricating a vertical-channel junction field-effect transistor includes forming an unintentionally doped GaN layer on a bulk GaN layer by metalorganic chemical vapor deposition, forming a Cr/SiO2 hard mask on the unintentionally doped GaN layer, patterning a fin by electron beam lithography, defining the Cr and SiO2 hard masks by reactive ion etching, improving a regrowth surface with inductively coupled plasma etching, removing hard mask residuals, regrowing a p-GaN layer, selectively etching the p-GaN layer, forming gate electrodes by electron beam evaporation, and forming source and drain electrodes by electron beam evaporation. The resulting vertical-channel junction field-effect transistor includes a doped GaN layer, an unintentionally doped GaN layer on the doped GaN layer, and a p-GaN regrowth layer on the unintentionally doped GaN layer. Portions of the p-GaN regrowth layer are separated by a vertical channel of the unintentionally doped GaN layer.

Abstract: A switching device including a GaN substrate; an unintentionally doped GaN layer on a first surface of the GaN substrate; a regrown unintentionally doped GaN layer on the unintentionally doped GaN layer; a regrowth interface between the unintentionally doped GaN layer and the regrown unintentionally doped GaN layer; a p-GaN layer on the regrown unintentionally doped GaN layer; a first electrode on the p-GaN layer; and a second electrode on a second surface of the GaN substrate.

Abstract: Fabricating a vertical-channel junction field-effect transistor includes forming an unintentionally doped GaN layer on a bulk GaN layer by metalorganic chemical vapor deposition, forming a Cr/SiO2 hard mask on the unintentionally doped GaN layer, patterning a fin by electron beam lithography, defining the Cr and SiO2 hard masks by reactive ion etching, improving a regrowth surface with inductively coupled plasma etching, removing hard mask residuals, regrowing a p-GaN layer, selectively etching the p-GaN layer, forming gate electrodes by electron beam evaporation, and forming source and drain electrodes by electron beam evaporation. The resulting vertical-channel junction field-effect transistor includes a doped GaN layer, an unintentionally doped GaN layer on the doped GaN layer, and a p-GaN regrowth layer on the unintentionally doped GaN layer. Portions of the p-GaN regrowth layer are separated by a vertical channel of the unintentionally doped GaN layer.

Abstract: A p-n diode includes a first electrode, a n-GaN layer on the first electrode, a p-GaN layer on the n-GaN layer, and a second electrode on a first portion of the p-GaN layer. A region of the p-GaN layer surrounding the electrode is a passivated region. Treating a GaN power device having a p-GaN layer includes covering a portion of the p-GaN layer with a metal layer, exposing the p-GaN layer to a hydrogen plasma, and thermally annealing the p-GaN layer, thereby passivating a region of the p-GaN layer proximate the metal layer.

Abstract: Fabricating a vertical-channel junction field-effect transistor includes forming an unintentionally doped GaN layer on a bulk GaN layer by metalorganic chemical vapor deposition, forming a Cr/SiO2 hard mask on the unintentionally doped GaN layer, patterning a fin by electron beam lithography, defining the Cr and SiO2 hard masks by reactive ion etching, improving a regrowth surface with inductively coupled plasma etching, removing hard mask residuals, regrowing a p-GaN layer, selectively etching the p-GaN layer, forming gate electrodes by electron beam evaporation, and forming source and drain electrodes by electron beam evaporation. The resulting vertical-channel junction field-effect transistor includes a doped GaN layer, an unintentionally doped GaN layer on the doped GaN layer, and a p-GaN regrowth layer on the unintentionally doped GaN layer. Portions of the p-GaN regrowth layer are separated by a vertical channel of the unintentionally doped GaN layer.

Abstract: A steep-slope (SS) field effect transistor (FET) including a FET having a source region and a drain region, and a threshold switching device in direct contact with the source region or the drain region of the FET. Fabricating the steep-slope (SS) field effect transistor (FET) includes fabricating an AlGaN/GaN metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT) having a source region and a drain region, depositing a first electrode layer directly on the source region or the drain region, depositing a threshold switching layer directly on the first electrode layer, and depositing a second electrode layer directly on the threshold switching layer.

Abstract: A switching device including a GaN substrate; an unintentionally doped GaN layer on a first surface of the GaN substrate; a regrown unintentionally doped GaN layer on the unintentionally doped GaN layer; a regrowth interface between the unintentionally doped GaN layer and the regrown unintentionally doped GaN layer; a p-GaN layer on the regrown unintentionally doped GaN layer; a first electrode on the p-GaN layer; and a second electrode on a second surface of the GaN substrate.

Abstract: A p-n diode includes a first electrode, a n-GaN layer on the first electrode, a p-GaN layer on the n-GaN layer, and a second electrode on a first portion of the p-GaN layer. A region of the p-GaN layer surrounding the electrode is a passivated region. Treating a GaN power device having a p-GaN layer includes covering a portion of the p-GaN layer with a metal layer, exposing the p-GaN layer to a hydrogen plasma, and thermally annealing the p-GaN layer, thereby passivating a region of the p-GaN layer proximate the metal layer.

Abstract: Fabricating a regrown GaN p-n junction includes depositing a n-GaN layer on a substrate including n+-GaN, etching a surface of the n-GaN layer to yield an etched surface, depositing a p-GaN layer on the etched surface, etching a portion of the n-GaN layer and a portion of the p-GaN layer to yield a mesa opposite the substrate, and passivating a portion of the p-GaN layer around an edge of the mesa. The regrown GaN p-n junction is defined at an interface between the n-GaN layer and the p-GaN layer. The regrown GaN p-n junction includes a substrate, a n-GaN layer on the substrate having an etched surface, a p-GaN layer on the etched surface, a mesa defined by an etched portion of the n-GaN layer and an etched portion of the p-GaN layer, and a passivated portion of the p-GaN layer around an edge of the mesa.

Abstract: A switching device including a GaN substrate; an unintentionally doped GaN layer on a first surface of the GaN substrate; a regrown unintentionally doped GaN layer on the unintentionally doped GaN layer; a regrowth interface between the unintentionally doped GaN layer and the regrown unintentionally doped GaN layer; a p-GaN layer on the regrown unintentionally doped GaN layer; a first electrode on the p-GaN layer; and a second electrode on a second surface of the GaN substrate.

Abstract: A pn heterojunction diode includes a p-GaN substrate, a layer of ?-Ga2O3 on a surface of the p-GaN substrate, an n contact disposed on a surface of the ?-Ga2O3 layer opposite the p-GaN substrate, and a p contact disposed on the surface of the p-GaN substrate and proximate the GaN substrate. Fabricating a pn heterojunction diode includes depositing a metal on a first surface of a ?-Ga2O3 wafer to form a first contact on the first surface of the ?-Ga2O3 wafer, adhering the first contact to an adhesive material, thereby exposing a second surface of the ?-Ga2O3 wafer, wherein the second surface is opposite the first surface, exfoliating layers of the ?-Ga2O3 wafer from the second surface to yield an exfoliated surface on the ?-Ga2O3 wafer, and contacting the exfoliated surface with a surface of a p-GaN substrate to yield a stack.

Abstract: A solar cell including a nonpolar m-plane GaN substrate, an n-type III-nitride layer, a III-nitride active region, and a p-type III-nitride layer. In one example, the solar cell includes a nonpolar m-plane GaN substrate, a Si-doped GaN layer, a multiplicity of InGaN/GaN layers, and and a Mg-doped GaN layer. A working temperature range of the solar cell is from room temperature to about 500° C., an external quantum efficiency of the solar cell increases by at least a factor of 2 from room temperature to 500° C., and a temperature coefficient of the solar cell is greater than zero up to 350° C.

Abstract: A steep-slope (SS) field effect transistor (FET) including a FET having a source region and a drain region, and a threshold switching device in direct contact with the source region or the drain region of the FET. Fabricating the steep-slope (SS) field effect transistor (FET) includes fabricating an AlGaN/GaN metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT) having a source region and a drain region, depositing a first electrode layer directly on the source region or the drain region, depositing a threshold switching layer directly on the first electrode layer, and depositing a second electrode layer directly on the threshold switching layer.

Abstract: An AlN Schottky barrier diode device on sapphire substrates is formed using metal organic chemical vapor deposition and demonstrates a kV-level breakdown voltage. The device structure employs a thin n-AlN epilayer as the device active region and thick resistive AlN underlayer as the insulator. At room temperature, the device was characterized by a low turn-on voltage of 1.2 V, a high on/off ratio of ˜105, a low ideality factor of 5.5, and a low reverse leakage current below 1 nA. Due to the ultra-wide bandgap of AlN, the device also exhibited excellent thermal stability over 500 K representing, therefore, a cost-effective route to high performance AlN based Schottky barrier diodes for high power, high voltage and high temperature applications.

Abstract: A switching device including a GaN substrate; an unintentionally doped GaN layer on a first surface of the GaN substrate; a regrown unintentionally doped GaN layer on the unintentionally doped GaN layer; a regrowth interface between the unintentionally doped GaN layer and the regrown unintentionally doped GaN layer; a p-GaN layer on the regrown unintentionally doped GaN layer; a first electrode on the p-GaN layer; and a second electrode on a second surface of the GaN substrate.

Abstract: An AlN Schottky barrier diode device on sapphire substrates is formed using metal organic chemical vapor deposition and demonstrates a kV-level breakdown voltage. The device structure employs a thin n-AlN epilayer as the device active region and thick resistive AlN underlayer as the insulator. At room temperature, the device was characterized by a low turn-on voltage of 1.2 V, a high on/off ratio of ˜105, a low ideality factor of 5.5, and a low reverse leakage current below 1 nA. Due to the ultra-wide bandgap of AlN, the device also exhibited excellent thermal stability over 500 K representing, therefore, a cost-effective route to high performance AlN based Schottky barrier diodes for high power, high voltage and high temperature applications.

Abstract: A method of performing a photoelectrochemical (PEC) etch on an exposed surface of a semipolar {20-2-1} III-nitride semiconductor, for improving light extraction from and for enhancing external efficiency of one or more active layers formed on or above the semipolar {20-2-1} III-nitride semiconductor.

Abstract: A light emitting diode structure of (Al,Ga,In)N thin films grown on a gallium nitride (GaN) semipolar substrate by metal organic chemical vapor deposition (MOCVD) that exhibits reduced droop. The device structure includes a quantum well (QW) active region of two or more periods, n-type superlattice layers (n-SLs) located below the QW active region, and p-type superlattice layers (p-SLs) above the QW active region. The present invention also encompasses a method of fabricating such a device.