Patents by Inventor Yujiro Tani

Yujiro Tani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110305402
    Abstract: The image processor 1 includes a frequency transform unit 12, an encoding unit 15, and a memory 4. The encoding unit 15 includes a DC processing unit 31 that generates a direct-current stream, an LP processing unit 32 that generates a low-frequency stream, an HP processing unit 33 that generates an upper high-frequency stream and a lower high-frequency stream, and an output unit 34 having output ports 41 to 44 to output the direct-current stream, the low-frequency stream, the upper high-frequency stream, and the lower high-frequency stream to the memory 4.
    Type: Application
    Filed: June 6, 2011
    Publication date: December 15, 2011
    Applicant: MegaChips Corporation
    Inventors: Yusuke MIZUNO, Yujiro TANI
  • Publication number: 20100293171
    Abstract: A first sorting unit includes a second sorting unit that sorts first frequency data for luminance based on a first table, a third sorting unit that sorts second frequency data for chrominance based on a second table, a fourth sorting unit that sorts third frequency data for chrominance based on a third table, and an updating unit that updates the second and third tables based on nonzero information on the first and second frequency data before the third and fourth sorting units start sorting.
    Type: Application
    Filed: April 13, 2010
    Publication date: November 18, 2010
    Applicant: MegaChips Corporation
    Inventors: Yujiro TANI, Kazuyuki TAKAHASHI
  • Publication number: 20100135589
    Abstract: An image processor includes a frequency transform unit performing frequency transform on a first pixel block as a target block, and a pre-filter performing prefiltering with a region which overlaps with plural unit regions for processing by the frequency transform unit as a unit region for processing, before frequency transform is performed. The pre-filter performs prefiltering on a second pixel block being a predetermined number of pixels each larger horizontally and vertically than the first pixel block as a target block. The pre-filter performs prefiltering sequentially on a plurality of second pixel blocks aligned horizontally. The number of pixel signals in a vertical direction within a group of pixel signals continuously inputted to the pre-filter for prefiltering is equal to the number of rows in the second pixel block.
    Type: Application
    Filed: March 10, 2009
    Publication date: June 3, 2010
    Applicant: MegaChips Corporation
    Inventors: Yujiro Tani, Atsushi Uchiyama
  • Publication number: 20100128999
    Abstract: A symbol generation part serially inputs a data string of quantization data. If quantization data of non-zero coefficient is inputted, respective information on an absolute value, a zero run and a sign of the non-zero coefficient are stored in registers. When quantization data of the next non-zero coefficient is inputted, the respective information on the absolute value, the zero run and the sign stored in the registers are updated. At that time, the contents of the registers which have been stored immediately before the input are outputted as symbol data of the immediately preceding non-zero coefficient.
    Type: Application
    Filed: March 23, 2009
    Publication date: May 27, 2010
    Applicant: MegaChips Corporation
    Inventors: Yujiro TANI, Yusuke Mizuno, Hideki Daian, Nobuhiro Minami, Masahiro Moriyama, Hiromu Hasegawa
  • Publication number: 20100111430
    Abstract: A sorting unit sorts a plurality of data sets of HP component having been processed by a decoding unit, selectively employing one of a first table corresponding to a first orientation of prediction and a second table corresponding to a second orientation of prediction in accordance with an orientation of prediction of HP component. The sorting unit includes an inverse prediction unit performing inverse prediction on data of LP component inputted from the decoding unit, a processing unit obtaining an orientation of prediction of HP component, based on the data of LP component after inverse prediction by the inverse prediction unit, and a selecting unit selecting one of the first and second tables, based on the orientation of prediction of HP component obtained by the processing unit.
    Type: Application
    Filed: October 2, 2009
    Publication date: May 6, 2010
    Applicant: MegaChips Corporation
    Inventors: Nobuhiro MINAMI, Yujiro Tani, Yusuke Mizuno, Hideki Daian, Masahiro Moriyama, Hiromu Hasegawa
  • Publication number: 20100104206
    Abstract: An image compression apparatus performs quantization of DC component data, low-pass component data and high-pass component data which are generated by frequency conversion of still image data. An extracting part extracts additional data and coding object data which is to be entropy coded, from quantization data. An entropy coding part performs entropy coding of the coding object data stored in a coding object data memory. An additional data processing part generates a flex bit from the additional data. A pattern information generation part acquires the coding object data directly from the extracting part, to generate pattern information indicating whether the coding object data is zero or not. A bit stream generation part outputs the pattern information, the coding object data and the flex bit in a predetermined order, to output a bit stream.
    Type: Application
    Filed: March 23, 2009
    Publication date: April 29, 2010
    Applicant: MegaChips Corporation
    Inventors: Masahiro Moriyama, Yujiro Tani, Yusuke Mizuno, Hideki Daian, Nobuhiro Minami, Hiromu Hasegawa
  • Publication number: 20100086223
    Abstract: A decoding unit includes a first processing unit including ND decoding units and decoding a group of Normal Data, a second processing unit decoding a group of Flex Bits, and a selector. The ND decoding units perform decoding of the group of Normal Data, stepwise varying a start position of decoding in the data stream, concurrently with decoding of the group of Flex Bits by the second processing unit. The selector selects one ND decoding unit with a start position of decoding being set at a position immediately following an end position of the group of Flex Bits, from the ND decoding units, based on a result of decoding of the group of Flex Bits.
    Type: Application
    Filed: March 17, 2009
    Publication date: April 8, 2010
    Applicant: MegaChips Corporation
    Inventors: Hideki DAIAN, Yujiro Tani, Yusuke Mizuno, Nobuhiro Minami, Masahiro Moriyama, Hiromu Hasegawa
  • Publication number: 20090238447
    Abstract: An image processor includes a frequency transform unit performing frequency transform independently on a luminance signal and plural chrominance signals and outputting an item of frequency data of the luminance signal and plural items of frequency data of the chrominance signals, and a quantization unit performing quantization independently on plural items of frequency data inputted from the frequency transform unit. The quantization unit performs quantization on one or plural specific items of frequency data corresponding to a signal with noise among the frequency data of the luminance signal and the chrominance signals, employing a quantization coefficient having a value greater than “1”, and performs quantization on frequency data apart from the specific items of frequency data, employing a quantization coefficient having a value “1”.
    Type: Application
    Filed: March 12, 2009
    Publication date: September 24, 2009
    Applicant: MegaChips Corporation
    Inventors: Atsushi UCHIYAMA, Yujiro Tani, Hiromu Hasegawa
  • Publication number: 20090238477
    Abstract: An image processor includes an encoder and a decoder. The encoder includes a frequency transform unit, a pre-filter, and a color conversion unit that converts a pixel signal of a first color space inputted from outside into a pixel signal of a second color space including a luminance signal and chrominance signals. The decoder includes a frequency inverse transform unit, a post-filter, and a color inverse conversion unit that inversely converts a pixel signal of the second color space into a pixel signal of the first color space. The pre-filter performs prefiltering on one or plural specific signals among the luminance and chrominance signals. The post-filter does not perform postfiltering on the above specific signals.
    Type: Application
    Filed: March 12, 2009
    Publication date: September 24, 2009
    Applicant: MegaChips Corporation
    Inventors: Atsushi UCHIYAMA, Yujiro TANI, Hiromu HASEGAWA
  • Publication number: 20090232393
    Abstract: In a first input step from outside to an image processor, a signal input unit inputs to a pre-filter a first part of first luminance signals inputted from outside, which is a part to be processed by the pre-filter in the first input step, and stores a remaining second part of the first luminance signals in the memory unit. In a second input step following the first input step, the signal input unit inputs to the pre-filter the second part of the first luminance signals read from the memory unit and a first part of second luminance signals inputted from outside, which is a part to be processed by the pre-filter in the second input step, and stores a remaining second part of the second luminance signals in the memory unit.
    Type: Application
    Filed: March 10, 2009
    Publication date: September 17, 2009
    Applicant: MegaChips Corporation
    Inventors: Yujiro TANI, Atsushi Uchiyama
  • Publication number: 20090103821
    Abstract: On the first hierarchical layer, the input image adjuster selects an overlap processing area from a frequency-unconverted image. On the first hierarchical layer, the overlap processor performs overlap processing on the overlap processing area, and holds the image data of the remaining processing areas, which cannot be frequency-converted. The remaining processing area, which is a linear area, can have an image width reduced down to the displacement between the overlap processing area and the block areas. The processes on the second hierarchical layer are identical to those on the first hierarchical layer. As a result, the encoder maximizes the advantage of the high performance achieved by hardware implementation.
    Type: Application
    Filed: October 6, 2008
    Publication date: April 23, 2009
    Applicant: MegaChips Corporation
    Inventor: Yujiro TANI