Patents by Inventor Yujun Li
Yujun Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140377194Abstract: The present invention provides an oral care composition containing (a) a zinc citrate; and (b) a surface-active organophosphate compound. The present invention also relates to a method of preventing a stain from depositing on a tooth surface or other oral surfaces. The present invention further relates to a method of demonstrating stain-proof efficacy of an oral care composition, as well as a demonstration product comprising a substrate coated with hydroxyapatite.Type: ApplicationFiled: June 24, 2014Publication date: December 25, 2014Inventors: Ross Strand, Yujun Li, Yiqun Zhang, Xiaoxiao Li
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Publication number: 20140377315Abstract: The present invention provides an oral care composition for encouraging proper tooth cleaning, containing particulate materials which can be breakable under a brushing action with a brushing force from 0.1N to 5N. The particulate materials can have a particle size distribution characterized by (1) a change ratio of mean particle size before and after the brushing action is at least 20%, (2) a change ratio of D90 before and after the brushing action is at least 20%, (3) at least 5% of the particulate materials have a particle size greater than 200 ?m before the brushing action, and (4) no more than 30% of the particulate materials have a particle size greater than 200 ?m after the brushing action. The oral care composition can have a viscosity ranging from 10 to 90 BKU.Type: ApplicationFiled: June 24, 2014Publication date: December 25, 2014Inventors: Ross Strand, Yujun Li, Yiqun Zhang, Xiaoxiao Li, Hanbo Bao
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Publication number: 20140002591Abstract: Embodiments of apparatuses, systems, and methods for a temporal hole filling are described. Specifically, an embodiment of the present invention may include a depth-based hole filling process that includes a background modeling technique (SGM). Beneficially, in such an embodiment, holes in the synthesized view may be filled effectively and efficiently.Type: ApplicationFiled: June 29, 2012Publication date: January 2, 2014Applicant: Hong Kong Applied Science and Technology Research Institute Co., Ltd.Inventors: Sun Wenxiu, Oscar C. Au, Lingfeng Xu, Yujun Li, Wei Hu, Lu Wang
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Patent number: 8614485Abstract: A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.Type: GrantFiled: December 23, 2008Date of Patent: December 24, 2013Assignee: International Business Machines CorporationInventors: Jochen Beintner, Gary B. Bronner, Ramachandra Divakaruni, Yujun Li
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Patent number: 7696539Abstract: A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal.Type: GrantFiled: June 18, 2008Date of Patent: April 13, 2010Assignee: International Business Machines CorporationInventors: Yujun Li, Kenneth T. Settlemyer, Jr., Jochen Beintner
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Patent number: 7666741Abstract: A method is presented for fabricating a non-planar field effect device. The method includes the production of a Si based material Fin structure that has a top surface substantially in parallel with a {111} crystallographic plane of the Si Fin structure, and the etching of the Si Fin structure with a solution which contains ammonium hydroxide (NH4OH). In this manner, due to differing etch rates in ammonium hydroxide of various Si based material crystallographic planes, the corners on the Fin structure become clipped, and angles between the horizontal and vertical planes of the Fin structure increase. A FinFET device with clipped, or rounded, corners is then fabricated to completion. In a typical embodiment the FinFET device is selected to be a silicon-on-insulator (SOI) device.Type: GrantFiled: January 17, 2006Date of Patent: February 23, 2010Assignee: International Business Machines CorporationInventors: Yujun Li, Kenneth T. Settlemyer, Jr., Jochen Beintner
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Publication number: 20100015078Abstract: Disclosed is a conditioning composition comprising: (a) from about 0.1% to about 10% of a surfactant system comprising: di- and mono-alkyl quaternized ammonium salt cationic surfactants; (b) from about 1% to about 15% of a high melting point fatty compound; (c) from about 0.1 % to about 20% of an aminosilicone; (d) from about 0.0001% to about 10% of a silicone resin; and (e) an aqueous carrier. The composition of the present invention can provide improved wet and dry conditioning benefits while providing chronic/long lasting color protection benefits.Type: ApplicationFiled: July 18, 2008Publication date: January 21, 2010Inventor: Yujun Li
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Publication number: 20090101995Abstract: A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.Type: ApplicationFiled: December 23, 2008Publication date: April 23, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jochen Beintner, Gary B. Bronner, Ramachandra Divakaruni, Yujun Li
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Patent number: 7470570Abstract: A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.Type: GrantFiled: November 14, 2006Date of Patent: December 30, 2008Assignee: International Business Machines CorporationInventors: Jochen Beintner, Gary B. Bronner, Ramachandra Divakaruni, Yujun Li
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Publication number: 20080246059Abstract: A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal.Type: ApplicationFiled: June 18, 2008Publication date: October 9, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yujun Li, Kenneth T. Settlemyer, Jochen Beintner
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Patent number: 7410844Abstract: A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal.Type: GrantFiled: January 17, 2006Date of Patent: August 12, 2008Assignee: International Business Machines CorporationInventors: Yujun Li, Kenneth T. Settlemyer, Jr., Jochen Beintner
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Publication number: 20080111184Abstract: A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.Type: ApplicationFiled: November 14, 2006Publication date: May 15, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jochen Beintner, Gary B. Bronner, Ramachandra Divakaruni, Yujun Li
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Patent number: 7354822Abstract: A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell incorporates two gate materials having different work functions. The gate material near the storage node is n-type doped polysilicon. The gate material near the bit line diffusion is made of silicide or metal having a higher work function than the n-polysilicon. The novel device structure shows several advantages: the channel doping is reduced while maintaining a high Vt and a low sub-threshold leakage current; the carrier mobility improves with the reduced channel doping; the body effect of the device is reduced which improves the write back current; and the sub-threshold swing is reduced because of the low channel doping.Type: GrantFiled: October 26, 2006Date of Patent: April 8, 2008Assignee: International Business Machines CorporationInventors: Xiangdong Chen, Geng Wang, Yujun Li, Qiqing C. Ouyang
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Publication number: 20070298004Abstract: Disclosed is a conditioning composition comprising: an asymmetric di-alkyl ammonium salt cationic surfactant; a high melting point fatty compound; and an aqueous carrier. The composition of the present invention can provide improved ease-to-rinse feel while maintaining conditioning benefits.Type: ApplicationFiled: June 20, 2007Publication date: December 27, 2007Inventor: Yujun Li
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Patent number: 7294879Abstract: A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell incorporates two gate materials having different work functions. The gate material near the storage node is n-type doped polysilicon. The gate material near the bit line diffusion is made of silicide or metal having a higher work function than the n-polysilicon. The novel device structure shows several advantages: the channel doping is reduced while maintaining a high Vt and a low sub-threshold leakage current; the carrier mobility improves with the reduced channel doping; the body effect of the device is reduced which improves the write back current; and the sub-threshold swing is reduced because of the low channel doping.Type: GrantFiled: July 18, 2003Date of Patent: November 13, 2007Assignee: International Business Machines CorporationInventors: Xiangdong Chen, Geng Wang, Yujun Li, Qiqing C. Ouyang
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Publication number: 20070166900Abstract: A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal.Type: ApplicationFiled: January 17, 2006Publication date: July 19, 2007Applicant: International Business Machines CorporationInventors: Yujun Li, Kenneth Settlemyer, Jochen Beintner
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Publication number: 20070167024Abstract: A method is presented for fabricating a non-planar field effect device. The method includes the production of a Si based material Fin structure that has a top surface substantially in parallel with a {111} crystallographic plane of the Si Fin structure, and the etching of the Si Fin structure with a solution which contains ammonium hydroxide (NH4OH). In this manner, due to differing etch rates in ammonium hydroxide of various Si based material crystallographic planes, the corners on the Fin structure become clipped, and angles between the horizontal and vertical planes of the Fin structure increase. A FinFET device with clipped, or rounded, corners is then fabricated to completion. In a typical embodiment the FinFET device is selected to be a silicon-on-insulator (SOI) device.Type: ApplicationFiled: January 17, 2006Publication date: July 19, 2007Applicant: International Business Machines CorporationInventors: Yujun Li, Kenneth Settlemyer, Jochen Beintner
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Publication number: 20070051996Abstract: A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell incorporates two gate materials having different work functions. The gate material near the storage node is n-type doped polysilicon. The gate material near the bit line diffusion is made of silicide or metal having a higher work function than the n-polysilicon. The novel device structure shows several advantages: the channel doping is reduced while maintaining a high Vt and a low sub-threshold leakage current; the carrier mobility improves with the reduced channel doping; the body effect of the device is reduced which improves the write back current; and the sub-threshold swing is reduced because of the low channel doping.Type: ApplicationFiled: October 26, 2006Publication date: March 8, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Xiangdong Chen, Geng Wang, Yujun Li, Qiqing Ouyang
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Patent number: 7129564Abstract: The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g.Type: GrantFiled: February 17, 2005Date of Patent: October 31, 2006Assignee: International Business Machines CorporationInventors: Jochen Beintner, Yujun Li, Naim Moumen, Porshia Shane Wrschka
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Publication number: 20060163631Abstract: A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell incorporates two gate materials having different work functions. The gate material near the storage node is n-type doped polysilicon. The gate material near the bit line diffusion is made of silicide or metal having a higher work function than the n-polysilicon. The novel device structure shows several advantages: the channel doping is reduced while maintaining a high Vt and a low sub-threshold leakage current; the carrier mobility improves with the reduced channel doping; the body effect of the device is reduced which improves the write back current; and the sub-threshold swing is reduced because of the low channel doping.Type: ApplicationFiled: July 18, 2003Publication date: July 27, 2006Applicant: International Business Machines CorporationInventors: Xiangdong Chen, Geng Wang, Yujun Li, Qiqing Ouyang