Patents by Inventor Yujun Li
Yujun Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20060157805Abstract: A structure and method of forming a notched gate MOSFET. A gate dielectric is formed on the surface of an active area on the semiconductor substrate. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium. The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer. One or more other processing steps are preferably performed in completing the transistor.Type: ApplicationFiled: November 4, 2005Publication date: July 20, 2006Applicants: INFINEON TECHNOLOGIES AG, International Business Machines CorporationInventors: Jochen Beintner, Yujun Li, Naim Moumen, Porshia Wrschka
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Publication number: 20060078528Abstract: Disclosed is a hair conditioning composition comprising: a cationic surfactant; a high melting point fatty compound; and an aqueous carrier; wherein the cationic surfactant, the high melting point fatty compound, and the aqueous carrier form a lamellar gel matrix; wherein the d-spacing of the lamellar layers is in the range of 33 nm or less; and wherein the composition has a yield stress of about 30 Pa or more at 26.7° C. The composition of the present invention can provide improved conditioning benefits, especially improved slippery feel during the application to wet hair.Type: ApplicationFiled: October 13, 2005Publication date: April 13, 2006Inventors: Jian-Zhong Yang, Koji Takata, Yujun Li, Hoyun Kim
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Patent number: 7018551Abstract: A method of forming integrated circuits having FinFET transistors includes a method of forming sub-lithographic fins, in which a mask defining a block of silicon including a pair of fins in reduced in width or pulled back by the thickness of one fin on each side, after which a second mask is formed around the first mask, so that after the first mask is removed, an aperture remains in the second mask having the width of the separation distance between the pair of fins. When the silicon is etched through the aperture, the fins are protected by the second mask, thereby defining fin thickness by the pullback step. An alternative method uses lithography of opposite polarity, first defining the central etch aperture between the two fins lithographically, then expanding the width of the aperture by a pullback step, so that filling the widened aperture with an etch-resistant plug defines the outer edges of the pair of fins, thereby setting the fin width without an alignment kstep.Type: GrantFiled: December 9, 2003Date of Patent: March 28, 2006Assignee: International Business Machines CorporationInventors: Jochen C. Beintner, Dureseti Chidambarrao, Yujun Li, Kenneth T. Settlemyer, Jr.
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Patent number: 7015552Abstract: A dual work function semiconductor structure with borderless contact and method of fabricating the same are presented. The structure may include a field effect transistor (FET) having a substantially cap-free gate and a conductive contact to a diffusion adjacent to the cap-free gate, wherein the conductive contact is borderless to the gate. Because the structure is a dual work function structure, the conductive contact is allowed to extend over the cap-free gate without being electrically connected thereto.Type: GrantFiled: April 4, 2005Date of Patent: March 21, 2006Assignee: International Business Machines CorporationInventors: Qiuyi Ye, William R. Tonti, Yujun Li
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Patent number: 6964892Abstract: An N-channel metal oxide semiconductor (NMOS) driver circuit (and method for making the same), includes a boost gate stack formed on a substrate and having a source and drain formed by a low concentration implantation, and an N-driver coupled to the boost gate stack.Type: GrantFiled: May 28, 2002Date of Patent: November 15, 2005Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Rama Divakaruni, Louis Lu-Chen Hsu, Yujun Li
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Publication number: 20050199966Abstract: A dual work function semiconductor structure with borderless contact and method of fabricating the same are presented. The structure may include a field effect transistor (FET) having a substantially cap-free gate and a conductive contact to a diffusion adjacent to the cap-free gate, wherein the conductive contact is borderless to the gate. Because the structure is a dual work function structure, the conductive contact is allowed to extend over the cap-free gate without being electrically connected thereto.Type: ApplicationFiled: April 4, 2005Publication date: September 15, 2005Applicant: International Business Machines CorporationInventors: Qiuyi Ye, William Tonti, Yujun Li
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Patent number: 6930004Abstract: A method of formation of a deep trench vertical transistor is provided. A deep trench with a sidewall in a doped semiconductor substrate is formed. The semiconductor substrate includes a counterdoped drain region in the surface thereof and a channel alongside the sidewall. The drain region has a top level and a bottom level. A counterdoped source region is formed in the substrate juxtaposed with the sidewall below the channel. A gate oxide layer is formed on the sidewalls of the trench juxtaposed with a gate conductor. Perform the step of recessing the gate conductor below the bottom level of the drain region followed by performing angled ion implantation at an angle ?+? with respect to vertical of a counterdopant into the channel below the source region and performing angled ion implantation at an angle ? with respect to vertical of a dopant into the channel below the source.Type: GrantFiled: August 13, 2003Date of Patent: August 16, 2005Assignee: International Business Machines CorporationInventors: Geng Wang, Kevin Mcstay, Mary Elizabeth Weybright, Yujun Li, Dureseti Chidambarrao
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Publication number: 20050158927Abstract: The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g.Type: ApplicationFiled: February 17, 2005Publication date: July 21, 2005Inventors: Jochen Beintner, Yujun Li, Naim Moumen, Porshia Wrschka
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Patent number: 6908815Abstract: A dual work function semiconductor structure with borderless contact and method of fabricating the same are presented. The structure may include a field effect transistor (FET) having a substantially cap-free gate and a conductive contact to a diffusion adjacent to the cap-free gate, wherein the conductive contact is borderless to the gate. Because the structure is a dual work function structure, the conductive contact is allowed to extend over the cap-free gate without being electrically connected thereto.Type: GrantFiled: July 22, 2003Date of Patent: June 21, 2005Assignee: International Business Machines CorporationInventors: Qiuyi Ye, William R. Tonti, Yujun Li
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Patent number: 6905976Abstract: The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g.Type: GrantFiled: May 6, 2003Date of Patent: June 14, 2005Assignee: International Business Machines CorporationInventors: Jochen Beintner, Yujun Li, Naim Moumen, Porshia Shane Wrschka
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Publication number: 20050121412Abstract: A method of forming integrated circuits having FinFET transistors includes a method of forming sub-lithographic fins, in which a mask defining a block of silicon including a pair of fins in reduced in width or pulled back by the thickness of one fin on each side, after which a second mask is formed around the first mask, so that after the first mask is removed, an aperture remains in the second mask having the width of the separation distance between the pair of fins. When the silicon is etched through the aperture, the fins are protected by the second mask, thereby defining fin thickness by the pullback step. An alternative method uses lithography of opposite polarity, first defining the central etch aperture between the two fins lithographically, then expanding the width of the aperture by a pullback step, so that filling the widened aperture with an etch-resistant plug defines the outer edges of the pair of fins, thereby setting the fin width without an alignment kstep.Type: ApplicationFiled: December 9, 2003Publication date: June 9, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jochen Beintner, Dureseti Chidambarrao, Yujun Li, Kenneth Settlemyer
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Publication number: 20050037561Abstract: A method of formation of a deep trench vertical transistor is provided. A deep trench with a sidewall in a doped semiconductor substrate is formed. The semiconductor substrate includes a counterdoped drain region in the surface thereof and a channel alongside the sidewall. The drain region has a top level and a bottom level. A counterdoped source region is formed in the substrate juxtaposed with the sidewall below the channel. A gate oxide layer is formed on the sidewalls of the trench juxtaposed with a gate conductor.Type: ApplicationFiled: August 13, 2003Publication date: February 17, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Geng Wang, Kevin McStay, Mary Weybright, Yujun Li, Dureseti Chidambarrao
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Publication number: 20040223938Abstract: Disclosed is a hair conditioning composition comprising by weight: (a) 0.01-10% of a mono-long alkyl quaternized ammonium salt cationic surfactant; (b) 2-20% of a high melting point fatty compound; (c) 0.0014% of a polysorbate; and (d) an aqueous carrier. The hair conditioning composition of the present invention can provide clean feel during and after rinsing the hair, while providing improved conditioning benefits to the hair.Type: ApplicationFiled: April 16, 2004Publication date: November 11, 2004Inventors: Yujun Li, Jian-Zhong Yang, Jun Hasegawa
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Publication number: 20040222498Abstract: The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g.Type: ApplicationFiled: May 6, 2003Publication date: November 11, 2004Applicants: International Business Machines Corporation, Infineon Technologies North America Corp.Inventors: Jochen Beintner, Yujun Li, Naim Moumen, Porshia Shane Wrschka
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Publication number: 20040108555Abstract: A dual work function semiconductor structure with borderless contact and method of fabricating the same are presented. The structure may include a field effect transistor (FET) having a substantially cap-free gate and a conductive contact to a diffusion adjacent to the cap-free gate, wherein the conductive contact is borderless to the gate. Because the structure is a dual work function structure, the conductive contact is allowed to extend over the cap-free gate without being electrically connected thereto.Type: ApplicationFiled: July 22, 2003Publication date: June 10, 2004Applicant: International Business Machines CorporationInventors: Qiuyi Ye, William R. Tonti, Yujun Li
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Publication number: 20040000660Abstract: A reaction mixture that is especially suited to generate heat in a controllable manner. The reaction mixture includes exothermic generating particles having a water soluble coating made from polyethylene glycol with a molecular weight between 2000 and 6000; a volatile component, a buffer, an anti-foaming agent, and optionally including an aqueous solution and a thickening agent. The reaction components are mixed together and the mixture increases in temperature to a Set Temperature within a predetermined time, and the mixture remains at the Set Temperature for a longer period of time. In this manner, volatile components can be controllably released to the surrounding environment. The volatile components can be, for example, a perfume, a fragrance, an insect repellent, a fumigant, a disinfectant, a bactericide, an insecticide, a pesticide, a germicide, an acaricide, a sterilizer, a deodorizer, a fogging agent and mixtures of these. Apparatuses and methods that use these reaction mixtures are also disclosed.Type: ApplicationFiled: August 20, 2003Publication date: January 1, 2004Applicant: The Procter & Gamble CompanyInventor: Yujun Li
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Patent number: 6642584Abstract: A dual work function semiconductor structure with borderless contact and method of fabricating the same are presented. The structure may include a field effect transistor (FET) having a substantially cap-free gate and a conductive contact to a diffusion adjacent to the cap-free gate, wherein the conductive contact is borderless to the gate. Because the structure is a dual work function structure, the conductive contact is allowed to extend over the cap-free gate without being electrically connected thereto.Type: GrantFiled: January 30, 2001Date of Patent: November 4, 2003Assignee: International Business Machines CorporationInventors: Qiuyi Ye, William R. Tonti, Yujun Li
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Patent number: 6528855Abstract: A MOSFET having a new source/drain (S/D) structure is particularly adapted to smaller feature sizes of modern CMOS technology. The S/D conductors are located on the shallow trench isolation (STI) to achieve low junction leakage and low junction capacitance. The S/D junction depth is defined by an STI etch step (according to a first method of making the MOSFET) or a silicon etch step (according to a second method of making the MOSFET). By controlling the etch depth, a very shallow junction depth is achieved. There is a low variation of gate length, since the gate area is defined by etching crystal silicon, not by etching polycrystalline silicon. There is a low aspect ratio between the gate and the S/D, since the gate conductor and the source and drain conductors are aligned on same level. A suicide technique is applied to the source and drain for low parasitic resistance; however, this will not result in severe S/D junction leakage, since the source and drain conductors sit on the STI.Type: GrantFiled: July 24, 2001Date of Patent: March 4, 2003Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Qiuyi Ye, William Tonti, Yujun Li, Jack A. Mandelman
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Publication number: 20030020120Abstract: A MOSFET having a new source/drain (S!D) structure is particularly adapted to smaller feature sizes of modern CMOS technology. The S/D conductors are located on the shallow trench isolation (STI) to achieve low junction leakage and low junction capacitance. The S/D junction depth is defined by an STI etch step (according to a first method of making the MOSFET) or a silicon etch step (according to a second method of making the MOSFET). By controlling the etch depth, a very shallow junction depth is achieved. There is a low variation of gate length, since the gate area is defined by etching crystal silicon, not by etching polycrystalline silicon. There is a low aspect ratio between the gate and the S/D, since the gate conductor and the source and drain conductors are aligned on same level. A suicide technique is applied to the source and drain for low parasitic resistance; however, this will not result in severe S/D junction leakage, since the source and drain conductors sit on the STI.Type: ApplicationFiled: July 24, 2001Publication date: January 30, 2003Applicant: Infineon Technologies North America Corp.Inventors: Qiuyi Ye, William Tonti, Yujun Li, Jack A. Mandelman
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Publication number: 20030003061Abstract: Disclosed are oral compositions comprising: (a) an effective amount of one or more linear polyphosphates having an average chain length of about 4 or more; (b) from about 0.15% to about 5% of a fluoride ion source; (c) from about 0.1% to about 15% of a stannous ion source; (d) an effective amount of a buffering agent; (e) from about 6% to about 70% of an abrasive polishing material containing less than 23% calcium; and (f) from about 40% to about 99% of one or more aqueous carriers; wherein the oral composition has a total water content of from about 1% to about 20%.Type: ApplicationFiled: August 14, 2002Publication date: January 2, 2003Applicant: The Procter & Gamble CompanyInventors: Jiang Yue, Sekhar Mitra, Yujun Li, Hsiang-Kuen Mao, Baoan Li