Patents by Inventor Yu-Kai Wang

Yu-Kai Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240424528
    Abstract: A polymer plastic front plate comprises: a plastic substrate and a hard coating layer formed on an adhesion surface of the plastic substrate. The hard coating layer comprises: organic-inorganic hybrid UV oligomer, high Tg UV resin additive, a plurality of dispersed flaky nano inorganic material, and photo initiator, so as to form a gas barrier hard coating layer with high surface dyne value (>44 dyne) on the adhesion surface of the plastic substrate. It not only has good ink printability and OCA adhesiveness, but also inhibits the diffusion of fugitive gas from polymer plastic front plates during high-temperature, high-temperature and high-humidity, high-low temperature thermal shocks and other harsh automotive industry environmental tests. The gas can be avoided from entering the OCA layer, thereby solving the problems of bubbles and delamination after the environmental tests are performed.
    Type: Application
    Filed: September 9, 2024
    Publication date: December 26, 2024
    Applicant: ENFLEX CORPORATION
    Inventors: Hsin Yuan CHEN, Chun Kai WANG, Yu Ling CHIEN
  • Patent number: 12176828
    Abstract: An energy storage device and a method thereof for supplying power are provided. Control a power conversion circuit to lower an AC output voltage during a preset period to a preset voltage, control the power conversion circuit to change from outputting the preset voltage to outputting a surge voltage, so that the power conversion circuit enters a surge generation period, and determine whether to turn off the energy storage device according to whether an output terminal of the power conversion circuit generating a surge current during the surge generation period.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: December 24, 2024
    Assignee: Merry Electronics(Shenzhen) Co., Ltd.
    Inventors: Yung-Hsiang Liu, Wei-Kang Liang, Yu-Kai Wang
  • Patent number: 12176465
    Abstract: A light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer; one or multiple vias penetrating the active layer and the second semiconductor layer to expose the first semiconductor layer; a first contact layer covering the one or multiple vias; a third insulating layer including a first group of one or multiple third insulating openings on the second semiconductor layer to expose the first contact layer; a first pad on the semiconductor stack and covering the first group of one or multiple third insulating openings; and a second pad on the semiconductor stack and separated from the first pad with a distance, wherein the second pad is formed at a position other than positions of the one or multiple vias in a top view of the light-emitting device.
    Type: Grant
    Filed: April 20, 2023
    Date of Patent: December 24, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Hsing Chen, Jia-Kuen Wang, Tzu-Yao Tseng, Bo-Jiun Hu, Tsung-Hsun Chiang, Wen-Hung Chuang, Kuan-Yi Lee, Yu-Ling Lin, Chien-Fu Shen, Tsun-Kai Ko
  • Patent number: 12174042
    Abstract: A UAV (unmanned aerial vehicle) including a first barometer and a processing unit is provided. The first barometer provides a first air pressure value. The processing unit is coupled to the first barometer for receiving the first air pressure value from the first barometer, performing timing-synchronization on the first air pressure value provided by the first barometer and an external reference air pressure value provided by an external reference barometer to obtain a timing-synchronized first air pressure value and recalculating the timing-synchronized first air pressure value to generate a compensated air pressure value, wherein the processing unit performs data fusion calculation on the first air pressure value, the compensated air pressure value and a sensor data to obtain a target fused data and real-timely controls the altitude and the posture of the UAV according to the target fused data.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: December 24, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yi-Lun Wen, Yu-Kai Wang
  • Publication number: 20240423095
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to the MTJ and extended to overlap a top surface of the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is adjacent to the top electrode and the MTJ and on the second IMD layer and a top surface of the cap layer is higher than a top surface of the first IMD layer.
    Type: Application
    Filed: August 26, 2024
    Publication date: December 19, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Hung-Yueh Chen, Yu-Ping Wang
  • Patent number: 12165873
    Abstract: In a method of manufacturing a semiconductor device, a mask pattern is formed over a target layer to be etched, and the target layer is etched by using the mask pattern as an etching mask. The etching is performed by using an electron cyclotron resonance (ECR) plasma etching apparatus, the ECR plasma etching apparatus includes one or more coils, and a plasma condition of the ECR plasma etching is changed during the etching the target layer by changing an input current to the one or more coils.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: En-Ping Lin, Yu-Ling Ko, I-Chung Wang, Yi-Jen Chen, Sheng-Kai Jou, Chih-Teng Liao
  • Patent number: 12155249
    Abstract: An energy storage device and a method thereof are provided. The power transfer circuit transfers a DC voltage provided by a battery module into an AC output voltage to provide the AC output voltage to an output end of the power transfer circuit for providing power to a load. When the AC output voltage is at a default phase, the power transfer circuit is disabled in a default period, and whether the energy storage device may be shut down is determined according to a voltage difference of the AC output voltage sensed by a sensing circuit during the default period.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: November 26, 2024
    Assignee: Merry Electronics(Shenzhen) Co., Ltd.
    Inventors: Yung-Hsiang Liu, Wei-Kang Liang, Yu-Kai Wang
  • Patent number: 12155902
    Abstract: Interaction is created between users and streamers even when the users give gifts to the streamers outside live-streams. Provided is a terminal of a user, which includes: one or more processors; and memory storing one or more computer programs configured to be executed by the one or more processors. The one or more computer programs include instructions for: receiving, from the user, an instruction to use a gift for a streamer while the user is not participating in a live-stream of the streamer; and causing an output unit to output an effect corresponding to the use of the gift by the user while the streamer is live-streaming.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: November 26, 2024
    Assignee: 17LIVE Japan Inc.
    Inventors: Yu-Shan Yang, Yung-Chi Hsu, Sheng-Kai Hsu, Ching-Jan Wang, Yun-An Lin
  • Patent number: 12156478
    Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.
    Type: Grant
    Filed: February 15, 2023
    Date of Patent: November 26, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Chen-Yi Weng, Jing-Yin Jhang, Yu-Ping Wang, Hung-Yueh Chen
  • Publication number: 20240387252
    Abstract: A semiconductor structure including a substrate, a first dielectric layer, a first conductive feature, an etch stop layer, a second dielectric layer and a second conductive feature is provided. The first dielectric layer is disposed over the substrate. The first conductive feature is disposed in the first dielectric layer. The etch stop layer is disposed over the first dielectric layer and the first conductive feature, wherein the etch stop layer comprises a metal-containing layer and a silicon-containing layer, the metal-containing layer is located between the first dielectric layer and the silicon-containing layer, the metal-containing layer comprises a nitride-containing region and an oxide-containing region, and the nitride-containing region contacts the first conductive feature. The second dielectric layer is disposed over the etch stop layer. The second conductive feature penetrates the second dielectric layer and electrically connects with the first conductive feature.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Kai Lin, Su-Jen Sung, Tze-Liang Lee, Jen-Hung Wang
  • Publication number: 20240387163
    Abstract: A method for drying a wafer includes a cleaning step, a liquid replacing step, and a drying step. In the cleaning step, a workpiece located in a process chamber is cleaned with a cleaning solution. In the liquid replacing step, a drying agent in gas phase is compressed to convert into liquid phase, and the drying agent in liquid phase is introduced to the process chamber to replace the cleaning solution. In the drying step, the cleaning solution is discharged out of the process chamber, and then the drying agent is converted from liquid phase back to gas phase and is discharged out of the process chamber.
    Type: Application
    Filed: July 7, 2023
    Publication date: November 21, 2024
    Inventors: TING-CHANG CHANG, CHUAN-WEI KUO, SHENG-YAO CHOU, SHIH-KAI LIN, HUNG-MING KUO, YU-BO WANG, PEI-JUN SUN
  • Publication number: 20240379378
    Abstract: A semiconductor structure includes a metal gate structure including a gate dielectric layer and a gate electrode, a conductive layer disposed on the gate electrode, and a gate contact disposed on the conductive layer. The conductive layer extends from a position below a top surface of the metal gate structure to a position above the top surface of the metal gate structure. The gate electrode includes at least a first metal, and the conductive layer includes at least the first metal and a second metal different from the first metal. Laterally the conductive layer is fully between opposing sidewalls of the metal gate structure.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Pang-Sheng Chang, Yu-Feng Yin, Chao-Hsun Wang, Kuo-Yi Chao, Fu-Kai Yang, Mei-Yun Wang, Feng-Yu Chang, Chen-Yuan Kao, Chia-Yang Hung, Chia-Sheng Chang, Shu-Huei Suen, Jyu-Horng Shieh, Sheng-Liang Pan, Jack Kuo-Ping Kuo, Shao-Jyun Wu
  • Publication number: 20240371649
    Abstract: A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Inventors: Che-Lun Chang, Pin-Chuan Su, Hsin-Chieh Huang, Ming-Yuan Wu, Tzu kai Lin, Yu-Wen Wang, Che-Yuan Hsu
  • Publication number: 20240365563
    Abstract: A semiconductor device including a magnetic tunneling junction (MTJ) and a hard mask on a substrate, a first inter-metal dielectric (IMD) layer around the MTJ, a first metal interconnection adjacent to the MTJ, a first barrier layer and a channel layer on the first IMD layer to directly contact the hard mask and electrically connect the MTJ and the first metal interconnection, and a stop layer around the channel layer.
    Type: Application
    Filed: July 3, 2024
    Publication date: October 31, 2024
    Applicant: UNITED MICROELECTRONICS CORP
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Jing-Yin Jhang, Yu-Ping Wang, Hung-Yueh Chen, Wei Chen
  • Patent number: 12131911
    Abstract: A method of forming a semiconductor device includes forming a first epitaxial layer over a substrate to form a wafer, depositing a dielectric layer over the first epitaxial layer, patterning the dielectric layer to form an opening, etching the first epitaxial layer through the opening to form a recess, forming a second epitaxial layer in the recess, etching the dielectric layer to expose a top surface of the first epitaxial layer, and planarizing the exposed top surface of the first epitaxial layer and a top surface of the second epitaxial layer.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: October 29, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Lun Chang, Pin-Chuan Su, Hsin-Chieh Huang, Ming-Yuan Wu, Tzu kai Lin, Yu-Wen Wang, Che-Yuan Hsu
  • Patent number: 12109587
    Abstract: A polymer plastic front plate comprises: a plastic substrate and a hard coating layer formed on an adhesion surface of the plastic substrate. The hard coating layer comprises: organic-inorganic hybrid UV oligomer, high Tg UV resin additive, a plurality of dispersed flaky nano inorganic material, and photo initiator, so as to form a gas barrier hard coating layer with high surface dyne value (>44 dyne) on the adhesion surface of the plastic substrate. It not only has good ink printability and OCA adhesiveness, but also inhibits the diffusion of fugitive gas from polymer plastic front plates during high-temperature, high-temperature and high-humidity, high-low temperature thermal shocks and other harsh automotive industry environmental tests. The gas can be avoided from entering the OCA layer, thereby solving the problems of bubbles and delamination after the environmental tests are performed.
    Type: Grant
    Filed: October 17, 2023
    Date of Patent: October 8, 2024
    Assignee: ENFLEX CORPORATION
    Inventors: Hsin Yuan Chen, Chun Kai Wang, Yu Ling Chien
  • Publication number: 20240332076
    Abstract: Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.
    Type: Application
    Filed: June 10, 2024
    Publication date: October 3, 2024
    Inventors: Wei-Yip Loh, Chih-Wei Chang, Hong-Mao Lee, Chun-Hsien Huang, Yu-Ming Huang, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Yu-Kai Chen, Yu-Wen Cheng
  • Patent number: 12108680
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to the MTJ and extended to overlap a top surface of the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is adjacent to the top electrode and the MTJ and on the second IMD layer and a top surface of the cap layer is higher than a top surface of the first IMD layer.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: October 1, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Hung-Yueh Chen, Yu-Ping Wang
  • Patent number: 12063792
    Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.
    Type: Grant
    Filed: June 8, 2023
    Date of Patent: August 13, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Jing-Yin Jhang, Yu-Ping Wang, Hung-Yueh Chen, Wei Chen
  • Patent number: 12046510
    Abstract: Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yip Loh, Chih-Wei Chang, Hong-Mao Lee, Chun-Hsien Huang, Yu-Ming Huang, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Yu-Kai Chen, Yu-Wen Cheng