Abstract: A method for protecting an exposed low-k surface is described. The method includes providing a substrate having a low-k insulation layer formed thereon and one or more mask layers overlying the low-k insulation layer with a pattern formed therein. Additionally, the method includes transferring the pattern in the one or more mask layers to the low-k insulation layer using one or more etching processes to form a trench and/or via structure in the low-k insulation layer. The method further includes forming an insulation protection layer on exposed surfaces of the trench and/or via structure during and/or following the one or more etching processes by exposing the substrate to a film forming compound containing C, H, and N. Thereafter, the method includes removing at least a portion of the one or more mask layers using a mask removal process.

Abstract: A site of interest extraction apparatus (10) includes: a passage section identification unit (4) that, for each user (20), renders a virtual line on a map using position information and direction information based on map information and on grid information identifying a plurality of sections, and identifies sections through which the virtual line passes, the position information and direction information being acquired for each user from a terminal device (21) owned by the user, and the virtual line being defined by the position information and direction information; an interest degree calculation unit (5) that, for each identified section, calculates an interest degree by adding a score in accordance with the virtual lines passing through the section; and a site of interest extraction unit (6) that selects one section based on the interest degrees and extracts the selected section as a site of interest to a plurality of users (20).

Abstract: A method for protecting an exposed low-k surface is described. The method includes providing a substrate having a low-k insulation layer formed thereon and one or more mask layers overlying the low-k insulation layer with a pattern formed therein. Additionally, the method includes transferring the pattern in the one or more mask layers to the low-k insulation layer using one or more etching processes to form a trench and/or via structure in the low-k insulation layer. The method further includes forming an insulation protection layer on exposed surfaces of the trench and/or via structure during and/or following the one or more etching processes by exposing the substrate to a film forming compound containing C, H, and N. Thereafter, the method includes removing at least a portion of the one or more mask layers using a mask removal process.

Abstract: The present invention is to provide a position information providing apparatus that allows the calculation of the confidence level of the measurement result with high accuracy. A position information providing apparatus includes a sensor data acquiring unit 110 acquiring sensor data, a feature amount calculating unit 120 calculating a feature amount from the sensor data, and a confidence level calculating unit 130 calculating a confidence level using the feature amount, wherein the sensor data is more than one, and the feature amount includes a statistical amount of more than one piece of the sensor data and an amount showing a form of the sensor data.

Abstract: The present invention provides a method for manufacturing a semiconductor device. In the method, a connection hole such as a via hole is formed in an interlayer insulating film by plasma etching with high etching uniformity regardless of the array density of connection holes. In the method, an upper layer film having a mask pattern is formed on the interlayer insulating film present on a substrate. A gas required for dehydration is then supplied to the substrate under the condition that an upper surface of the interlayer insulating film is exposed in order to remove moisture from the interlayer insulating film. A portion of the interlayer insulating film is etched to form a connection hole in which an electrical connection portion is to be embedded.

Abstract: A main power supply and a backup power supply have the same set voltage. To prevent electrical power from being supplied from the backup power supply to a load circuit, during a normal operation, a power supply control unit gives a standby instruction to the backup power supply so that the backup power supply is on standby at a voltage lower than that of the main power supply. When an AC power supply is stopped, the backup power supply is operated at the set voltage and the main power supply is stopped.

Abstract: An interest level estimation apparatus 10 is provided with an interest level estimation unit 11 that, using at least one of environmental information specifying an environment of every section within a specific space 100 and position information specifying a position of every section, and visitor number information specifying, for every section, the number of people visiting the section, estimates, for every section, a level of interest indicating a level to which people visiting the section are interested in the section.

Abstract: The present invention is an apparatus for manufacturing a semiconductor device comprising: a process vessel including a stage on which a substrate is placed, the substrate having a low dielectric constant film with a resist pattern being formed in an upper layer of the low dielectric constant film; an etching-gas supply unit that supplies an etching gas into the process vessel so as to etch the low dielectric constant film; an ashing-gas unit means that supplies an ashing gas into the process vessel so as to ash the resist pattern formed in the upper layer of the low dielectric constant film after the low dielectric constant film has been subjected to an etching process; a plasma generating means that generates a plasma by supplying an energy to the etching gas and the ashing gas in the process vessel; a unit that supplies a dipivaloylmethane gas into the process vessel, after the low dielectric constant film has been subjected to an ashing process, in order to recover a damage layer of the low dielectric con

Abstract: A method for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a patterned substrate containing metal surfaces and dielectric layer surfaces, and modifying the dielectric layer surfaces by exposure to a reactant gas containing a hydrophobic functional group, where the modifying substitutes a hydrophilic functional group in the dielectric layer surfaces with a hydrophobic functional group. The method further includes depositing metal-containing cap layers selectively on the metal surfaces by exposing the modified dielectric layer surfaces and the metal surfaces to a deposition gas containing metal-containing precursor vapor.

Abstract: The present invention relates to a method of manufacturing a semiconductor device using a substrate including an organic low dielectric constant film containing a silicon, a carbon, an oxygen, and a hydrogen, with a resist pattern being formed on an upper layer side of the low dielectric constant film. The method comprising: an etching step in which the low dielectric constant film is etched by a plasma; an ashing step following to the etching step, in which the resist pattern is ashed by a plasma that is rich in oxygen radicals in such a manner that a relative dielectric constant of the low dielectric constant film can become 5.2 or more; and a recovering step following to the ashing step, in which an organic gas is supplied to the low dielectric constant film so as to recovery a damage of the low dielectric constant film caused by the plasma.

Abstract: In a magnetic field generator for magnetron plasma generation which comprises a dipole-ring magnet with a plurality of columnar anisotropic segment magnets arranged in a ring-like manner, or in an etching apparatus and a method both of which utilize the magnetic field generator, the uniformity of plasma treatment over the entire surface of a wafer (workpiece) is improved by controlling the direction of the magnetic field relative to the working surface of the wafer (workpiece) which is subject to plasma treatment such as etching.

Abstract: A main power supply and a backup power supply have the same set voltage. To prevent electrical power from being supplied from the backup power supply to a load circuit, during a normal operation, a power supply control unit gives a standby instruction to the backup power supply so that the backup power supply is on standby at a voltage lower than that of the main power supply. When an AC power supply is stopped, the backup power supply is operated at the set voltage and the main power supply is stopped.

Abstract: A method for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a patterned substrate containing metal surfaces and dielectric layer surfaces, and modifying the dielectric layer surfaces by exposure to a reactant gas containing a hydrophobic functional group, where the modifying substitutes a hydrophilic functional group in the dielectric layer surfaces with a hydrophobic functional group. The method further includes depositing metal-containing cap layers selectively on the metal surfaces by exposing the modified dielectric layer surfaces and the metal surfaces to a deposition gas containing metal-containing precursor vapor.

Abstract: A processing method includes a gas having a Si—CH3 bond supplied into a processing chamber after a target substrate to be processed is loaded into the processing chamber; and a silylation process performed on the target substrate. The internal pressure of the chamber by the supply of the gas having the Si—CH3 bond and the gas supply time are set to be within ranges where the silylation process can be performed while the internal pressure of the chamber is decreased to reach an eligible pressure level where the wafer can be unloaded after the internal pressure of the chamber is increased up to a preset pressure by the supply of the gas.

Abstract: In a method for manufacturing a semiconductor device, a first high frequency power of a first frequency is applied to a processing gas to generate a plasma of the processing gas, a second high frequency power of a second frequency smaller than the first frequency is applied to a substrate to be processed. Further, a to-be-etched layer disposed under a resist film having a pattern of openings is etched by using the resist film as a mask, the to-be-etched layer being disposed on a surface of the substrate. In addition, dimensions of openings formed in the to-be-etched layer are controlled by varying an applied power of the first high frequency.

Abstract: The present invention relates to a method of manufacturing a semiconductor device using a substrate including an organic low dielectric constant film containing a silicon, a carbon, an oxygen, and a hydrogen, with a resist pattern being formed on an upper layer side of the low dielectric constant film. The method comprising: an etching step in which the low dielectric constant film is etched by a plasma; an ashing step following to the etching step, in which the resist pattern is ashed by a plasma that is rich in oxygen radicals in such a manner that a relative dielectric constant of the low dielectric constant film can become 5.2 or more; and a recovering step following to the ashing step, in which an organic gas is supplied to the low dielectric constant film so as to recovery a damage of the low dielectric constant film caused by the plasma.

Abstract: The present invention is an apparatus for manufacturing a semiconductor device comprising: a process vessel including a stage on which a substrate is placed, the substrate having a low dielectric constant film with a resist pattern being formed in an upper layer of the low dielectric constant film; an etching-gas supply unit that supplies an etching gas into the process vessel so as to etch the low dielectric constant film; an ashing-gas unit means that supplies an ashing gas into the process vessel so as to ash the resist pattern formed in the upper layer of the low dielectric constant film after the low dielectric constant film has been subjected to an etching process; a plasma generating means that generates a plasma by supplying an energy to the etching gas and the ashing gas in the process vessel; a unit that supplies a dipivaloylmethane gas into the process vessel, after the low dielectric constant film has been subjected to an ashing process, in order to recover a damage layer of the low dielectric con

Abstract: The present invention provides a method for manufacturing a semiconductor device. In the method, a connection hole such as a via hole is formed in an interlayer insulating film by plasma etching with high etching uniformity regardless of the array density of connection holes. In the method, an upper layer film having a mask pattern is formed on the interlayer insulating film present on a substrate. A gas required for dehydration is then supplied to the substrate under the condition that an upper surface of the interlayer insulating film is exposed in order to remove moisture from the interlayer insulating film. A portion of the interlayer insulating film is etched to form a connection hole in which an electrical connection portion is to be embedded.

Abstract: A processing method includes a gas having a Si—CH3 bond supplied into a processing chamber after a target substrate to be processed is loaded into the processing chamber; and a silylation process performed on the target substrate. The internal pressure of the chamber by the supply of the gas having the Si—CH3 bond and the gas supply time are set to be within ranges where the silylation process can be performed while the internal pressure of the chamber is decreased to reach an eligible pressure level where the wafer can be unloaded after the internal pressure of the chamber is increased up to a preset pressure by the supply of the gas.

Abstract: A method includes forming an etching mask having a predetermined circuit pattern on an Si-containing low dielectric constant film disposed on a semiconductor substrate; performing etching on the Si-containing low dielectric constant film through the etching mask by use of an F-containing gas, thereby forming a groove or hole; performing ashing by use of NH3 gas after said etching, thereby removing the etching mask; removing a by-product generated during said ashing; and then supplying a predetermined recovery gas, thereby recovering damage of the Si-containing low dielectric constant film caused before or in said removing the etching mask.