Abstract: According to one embodiment, a display device includes an insulating substrate, a first insulating film, a second insulating film, a third insulating film, a fourth insulating film, a fifth insulating film, a sixth insulating film, a color filter layer, a semiconductor layer disposed between the second insulating film and the third insulating film, and a gate electrode disposed between the third insulating film and the fourth insulating film, wherein the first, fourth, and sixth insulating films are formed of a silicon nitride, and the second, third, and fifth insulating films are formed of a silicon oxide.

Abstract: According to one embodiment, a liquid crystal panel includes substrates opposed to each other and paired. The liquid crystal panel includes a liquid crystal layer interposed between the substrates. The liquid crystal panel includes a sealed portion that includes bending corner portions at positions spaced from the outer edges of the substrates, and surrounds the periphery of the liquid crystal layer and bonds the substrates together. The liquid crystal panel includes main spacers that are interposed between the substrates at the position of the liquid crystal layer and hold the gap between the substrates. The liquid crystal panel includes auxiliary spacers that are interposed between the substrates to fill the portions between the outer side portions of the corner portions of the sealed portion and the outer edge sides of the substrates and hold the gap between the substrates.

Abstract: According to one embodiment, a semiconductor device includes, an oxide semiconductor layer including a channel region, and a source region and a drain region, a first insulation film covering the channel region and exposing the source region and the drain region, a first conductive layer including a gate electrode, and a first terminal electrode, a second insulation film covering the first conductive layer, the source region and the drain region, a second conductive layer including a source electrode, a drain electrode, and a second terminal electrode which is opposed to the first terminal electrode via the second insulation film, and a third insulation film interposed between the second insulation film, and the source electrode and the drain electrode.

Abstract: According to one embodiment, a method of manufacturing a thin-film transistor circuit substrate including forming an oxide semiconductor thin film above an insulative substrate, forming a gate insulation film and a gate electrode which are stacked on a first region of the oxide semiconductor thin film, and exposing from the gate insulation film a second region and a third region of the oxide semiconductor thin film, the second region and the third region being located on both sides of the first region of the oxide semiconductor thin film, forming an interlayer insulation film of silicon nitride including dangling bonds of silicon, the interlayer insulation film covering the second region and the third region of the oxide semiconductor thin film, the gate insulation film and the gate electrode, and forming a source electrode and a drain electrode.

Abstract: According to one embodiment, a liquid crystal panel includes substrates opposed to each other and paired. The liquid crystal panel includes a liquid crystal layer interposed between the substrates. The liquid crystal panel includes a sealed portion that includes bending corner portions at positions spaced from the outer edges of the substrates, and surrounds the periphery of the liquid crystal layer and bonds the substrates together. The liquid crystal panel includes main spacers that are interposed between the substrates at the position of the liquid crystal layer and hold the gap between the substrates. The liquid crystal panel includes auxiliary spacers that are interposed between the substrates to fill the portions between the outer side portions of the corner portions of the sealed portion and the outer edge sides of the substrates and hold the gap between the substrates.

Abstract: According to one embodiment, a semiconductor device includes, an oxide semiconductor layer including a channel region, and a source region and a drain region, a first insulation film covering the channel region and exposing the source region and the drain region, a first conductive layer including a gate electrode, and a first terminal electrode, a second insulation film covering the first conductive layer, the source region and the drain region, a second conductive layer including a source electrode, a drain electrode, and a second terminal electrode which is opposed to the first terminal electrode via the second insulation film, and a third insulation film interposed between the second insulation film, and the source electrode and the drain electrode.

Abstract: According to one embodiment, a method of manufacturing a thin-film transistor circuit substrate including forming an oxide semiconductor thin film above an insulative substrate, forming a gate insulation film and a gate electrode which are stacked on a first region of the oxide semiconductor thin film, and exposing from the gate insulation film a second region and a third region of the oxide semiconductor thin film, the second region and the third region being located on both sides of the first region of the oxide semiconductor thin film, forming an interlayer insulation film of silicon nitride including dangling bonds of silicon, the interlayer insulation film covering the second region and the third region of the oxide semiconductor thin film, the gate insulation film and the gate electrode, and forming a source electrode and a drain electrode.

Abstract: According to one embodiment, a method of manufacturing a thin-film transistor circuit substrate including forming an oxide semiconductor thin film above an insulative substrate, forming a gate insulation film and a gate electrode which are stacked on a first region of the oxide semiconductor thin film, and exposing from the gate insulation film a second region and a third region of the oxide semiconductor thin film, the second region and the third region being located on both sides of the first region of the oxide semiconductor thin film, forming an interlayer insulation film of silicon nitride including dangling bonds of silicon, the interlayer insulation film covering the second region and the third region of the oxide semiconductor thin film, the gate insulation film and the gate electrode, and forming a source electrode and a drain electrode.

Abstract: A negatively chargeable developer includes: negatively chargeable toner mother particles including at least binding resin and colorant; and an external additive that is externally added to a surface of the toner mother particles, wherein the external additive includes polymethyl methacrylate that is within a range from approximately 0.4 parts by weight to approximately 0.8 parts by weight inclusive per 100 parts by weight of the toner mother particles and that has positive chargeability.

Abstract: An image forming unit includes an image carrier carrying an electrostatic latent image on a surface thereof; a developer supply member supplying developer; a developer carrier carrying the developer supplied by the developer supply member on a surface thereof; and a developer layer forming member that includes a curvature part having a predetermined curvature radius, abutting the curvature part on the surface of the developer carrier to form a developer layer on the surface. The developer carrier attaches the developer layer to the electrostatic latent image to form a developer image on the surface of the image carrier, and a pressing parameter is within a range of 9.3×10?7 g·m2/s2 or more and 2.3×10?6 g·m2/s2 or less when the pressing parameter is determined by multiplying a linear pressure of the curvature part against the surface of the developer carrier, a square root of the curvature radius, and pi (?).

Abstract: A developer has a molecular weight distribution of its tetrahydrofuran soluble portion measured by a gel permeation chromatography. In the molecular weight distribution, the main peak is in a range from 2×103 to 3×104 weight-average molecular weight (Mw), the shoulder peak is in a range from 200 to 500 Mw, and a half-value width of the main peak is equal to or less than 50000. A glass-transition temperature Tg of the developer is a range from 55° C. to 80° C.

Abstract: A developer includes particles of developer base material containing a binder resin and external additive added to surfaces of the particles of developer base material. A loose bulk density is not smaller than 0.300 g/ml but not larger than 0.420 g/ml, and a release rate of the external additive from the particles of developer base material is not lower than 5% but not higher than 15%.

Abstract: According to one embodiment, a method of manufacturing a thin-film transistor circuit substrate including forming an oxide semiconductor thin film above an insulative substrate, forming a gate insulation film and a gate electrode which are stacked on a first region of the oxide semiconductor thin film, and exposing from the gate insulation film a second region and a third region of the oxide semiconductor thin film, the second region and the third region being located on both sides of the first region of the oxide semiconductor thin film, forming an interlayer insulation film of silicon nitride including dangling bonds of silicon, the interlayer insulation film covering the second region and the third region of the oxide semiconductor thin film, the gate insulation film and the gate electrode, and forming a source electrode and a drain electrode.

Abstract: Disclosed is a developer including at least a toner for developing electrostatic latent images. The toner includes toner base particles each containing at least one binder resin, and external additives for adhering to the outer surfaces of the toner base particles. The toner has a first triboelectric charge obtained by blow-off charge measurement at 20% relative humidity and a temperature of 10° C., and a second triboelectric charge obtained by blow-off charge measurement at 80% relative humidity and a temperature of 28° C. An absolute value of the difference between the first and second triboelectric charges is no larger than 20 ?C/g.

Abstract: A negatively chargeable developer includes: negatively chargeable toner mother particles including at least binding resin and colorant; and an external additive that is externally added to a surface of the toner mother particles, wherein the external additive includes polymethyl methacrylate that is within a range from approximately 0.4 parts by weight to approximately 0.8 parts by weight inclusive per 100 parts by weight of the toner mother particles and that has positive chargeability.

Abstract: A developing device is disposed facing an image bearing body that bears a latent image. The developing device includes a developer bearing body that bears a developer for developing the latent image. The developer includes mother particles and external additives. A liberation amount T (weight parts) of the external additives liberated from the mother particles with respect to 100 weight parts of the mother particles, a surface roughness Rz (m) of the developer bearing body, and a circumferential speed Vd (mm/s) of the developer bearing body satisfy the following relationships: 1.326×10?1?T?2.142×10?1 (weight parts), 7.1×10?6?Rz?15.0×10?6 (m), 161.5?Vd?189.2 (mm/s), and 4.98×10?6?(T×Rz/Vd)?1.99×10?5 (s).

Abstract: A developer has a molecular weight distribution of its tetrahydrofuran soluble portion measured by a gel permeation chromatography. In the molecular weight distribution, the main peak is in a range from 2×103 to 3×104 weight-average molecular weight (Mw), the shoulder peak is in a range from 200 to 500 Mw, and a half-value width of the main peak is equal to or less than 50000. A glass-transition temperature Tg of the developer is a range from 55° C. to 80° C.

Abstract: A developer includes a toner including a toner mother particle having a resin and a colorant and an external additive to be added to a surface of the toner mother particle. The toner has a volume average particle size of greater than or equal to 3.0 ?m and smaller than or equal to 7.0 ?m and has a surface roughness Rzjis of greater than or equal to 75.3 nm and smaller than or equal to 236.9 nm under observation using a scanning probe microscope. The external additive is titanium oxide having a particle size of greater than or equal to 10 nm and smaller than or equal to 100 nm.

Abstract: A developer includes a toner containing toner mother particles and external additives added to the toner mother particles. The toner mother particles contain at least a resin and a coloring agent. 1.5 to 3.0 weight parts of the external additives are added to 100 weight parts of the toner mother particles. The toner has a mean volume diameter in a range from 6.5 to 8.0 ?m, and a surface roughness Rzjis in a range from 75.3 to 236.9 nm as measured using a scanning probe microscope.

Abstract: A developing device is disposed facing an image bearing body that bears a latent image. The developing device includes a developer bearing body that bears a developer for developing the latent image. The developer includes mother particles and external additives. A liberation amount T (weight parts) of the external additives liberated from the mother particles with respect to 100 weight parts of the mother particles, a surface roughness Rz (m) of the developer bearing body, and a circumferential speed Vd (mm/s) of the developer bearing body satisfy the following relationships: 1.326×10?1?T?2.142×10?1(weight parts), 7.1×10?6?Rz?15.0×10?6(m), 161.5?Vd?189.2(mm/s), and 4.98×10?6?(T×Rz/Vd)?1.99×10?5(s).