Patents by Inventor Yuki Yanagisawa

Yuki Yanagisawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9478307
    Abstract: A memory device includes a memory cell which has one cell selection section and a storage section which is connected in series with respect to the cell selection section and which is selected as an access target for writing or reading by the cell selection section, in which the storage section is provided with a plurality of memory elements which are able to be written one time only and where information is held by changing resistance values in a non-written state and a written state.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: October 25, 2016
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Yuki Yanagisawa
  • Patent number: 9336895
    Abstract: A semiconductor unit with memory devices, each of the memory devices includes: a first semiconductor layer; second and third semiconductor layers; a first dielectric film and a first conductive film; first, second, and third electrodes electrically connected to the second semiconductor layer, the third semiconductor layer, and the first conductive film, respectively, the third electrode being electrically connected to the first electrode. In the memory devices, when a voltage equal to or higher than a predetermined threshold value is applied between the first and second electrodes, a filament that is a conductive path electrically linking the second and third semiconductor layers is formed in the region between the second and third semiconductor layers, and thereby, writing operation of information is performed.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: May 10, 2016
    Assignee: SONY CORPORATION
    Inventors: Yuki Yanagisawa, Shigeru Kanematsu, Matsuo Iwasaki
  • Publication number: 20150337244
    Abstract: Provided is a liquid detergent composition for clothing which is formed by blending (a) a nonionic surfactant represented by Formula (1), (b) an anionic surfactant represented by Formula (2), a predetermined amount of (c) an organic solvent having one or more hydroxyl groups, and water in which the mass ratio (b)/(a) of the blending amount of the component (b) to the blending amount of the component (a) is 0.
    Type: Application
    Filed: December 25, 2013
    Publication date: November 26, 2015
    Applicant: KAO CORPORATION
    Inventors: Ayako KITA, Yuki YANAGISAWA, Masataka MAKI
  • Publication number: 20150302932
    Abstract: A semiconductor unit with memory devices, each of the memory devices includes: a first semiconductor layer; second and third semiconductor layers; a first dielectric film and a first conductive film; first, second, and third electrodes electrically connected to the second semiconductor layer, the third semiconductor layer, and the first conductive film, respectively, the third electrode being electrically connected to the first electrode. In the memory devices, when a voltage equal to or higher than a predetermined threshold value is applied between the first and second electrodes, a filament that is a conductive path electrically linking the second and third semiconductor layers is formed in the region between the second and third semiconductor layers, and thereby, writing operation of information is performed.
    Type: Application
    Filed: April 8, 2013
    Publication date: October 22, 2015
    Inventors: Yuki Yanagisawa, Shigeru Kanematsu, Matsuo Iwasaki
  • Patent number: 9082823
    Abstract: A semiconductor device, includes: a first semiconductor layer having a first conductivity type; a pair of first electrodes arranged to be separated from each other in the first semiconductor layer; a second electrode provided on the first semiconductor layer between the pair of first electrodes with a dielectric film in between; and a pair of connection sections electrically connected to the pair of first electrodes, wherein one or both of the pair of first electrodes are divided into a first region and a second region, the first region and the second region being connected by a bridge section.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: July 14, 2015
    Assignee: Sony Corporation
    Inventors: Shoji Kobayashi, Yuki Yanagisawa
  • Publication number: 20150103579
    Abstract: A memory device includes a memory cell which has one cell selection section and a storage section which is connected in series with respect to the cell selection section and which is selected as an access target for writing or reading by the cell selection section, in which the storage section is provided with a plurality of memory elements which are able to be written one time only and where information is held by changing resistance values in a non-written state and a written state.
    Type: Application
    Filed: September 11, 2014
    Publication date: April 16, 2015
    Inventor: Yuki Yanagisawa
  • Publication number: 20140268984
    Abstract: Provided is a semiconductor device that includes: a storage element including a first terminal, a second terminal, and a third terminal, and in which a resistance state between the second terminal and the third terminal is changed from a high resistance state to a low resistance state based on a stress current that flows between the first terminal and the second terminal; and a fuse connected to the first terminal, and configured to change from a conductive state to a non-conductive state based on the stress current.
    Type: Application
    Filed: February 18, 2014
    Publication date: September 18, 2014
    Applicant: SONY CORPORATION
    Inventor: Yuki Yanagisawa
  • Publication number: 20140239441
    Abstract: A semiconductor device, includes: a first semiconductor layer having a first conductivity type; a pair of first electrodes arranged to be separated from each other in the first semiconductor layer; a second electrode provided on the first semiconductor layer between the pair of first electrodes with a dielectric film in between; and a pair of connection sections electrically connected to the pair of first electrodes, wherein one or both of the pair of first electrodes are divided into a first region and a second region, the first region and the second region being connected by a bridge section.
    Type: Application
    Filed: February 20, 2014
    Publication date: August 28, 2014
    Applicant: Sony Corporation
    Inventors: Shoji Kobayashi, Yuki Yanagisawa
  • Patent number: 8797782
    Abstract: An operation method of a semiconductor device, includes providing one or more memory elements each including a first semiconductor layer, second and third semiconductor layers, a dielectric film and a conductive film, a first electrode, a second electrode, and a third electrode, and performing operation of writing information on a memory element to be driven of the one or more memory elements. The operation of writing is performed by forming a filament in a region between the second and third semiconductor layers, which is a conductive path electrically linking these semiconductor layers, the filament being formed by causing a dielectric breakdown of at least a part of the dielectric film, through application of a voltage equal to or higher than a predetermined threshold between the second and third electrodes, thereby causing an electric current to flow between the conductive film and the third semiconductor layer.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: August 5, 2014
    Assignee: Sony Corporation
    Inventors: Shigeru Kanematsu, Yuki Yanagisawa, Matsuo Iwasaki
  • Patent number: 8611129
    Abstract: An operation method of a semiconductor device, includes providing one or more memory elements each including a first semiconductor layer of a first conductivity type, second and third semiconductor layers of a second conductivity type, which are disposed to be separated from each other in the first semiconductor layer, a first electrode electrically connected to the second semiconductor layer, and a second electrode electrically connected to the third semiconductor layer, and performing operation of writing information on a memory element to be driven of the one or more memory elements. The operation of writing is performed by forming a filament in a region between the second and third semiconductor layers, which is a conductive path electrically linking these semiconductor layers, through application of a voltage equal to or higher than a predetermined threshold between the first electrode and the second electrode.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: December 17, 2013
    Assignee: Sony Corporation
    Inventors: Shigeru Kanematsu, Yuki Yanagisawa, Matsuo Iwasaki
  • Publication number: 20120212991
    Abstract: An operation method of a semiconductor device, includes providing one or more memory elements each including a first semiconductor layer of a first conductivity type, second and third semiconductor layers of a second conductivity type, which are disposed to be separated from each other in the first semiconductor layer, a first electrode electrically connected to the second semiconductor layer, and a second electrode electrically connected to the third semiconductor layer, and performing operation of writing information on a memory element to be driven of the one or more memory elements. The operation of writing is performed by forming a filament in a region between the second and third semiconductor layers, which is a conductive path electrically linking these semiconductor layers, through application of a voltage equal to or higher than a predetermined threshold between the first electrode and the second electrode.
    Type: Application
    Filed: January 30, 2012
    Publication date: August 23, 2012
    Applicant: SONY CORPORATION
    Inventors: Shigeru Kanematsu, Yuki Yanagisawa, Matsuo Iwasaki
  • Publication number: 20120212992
    Abstract: An operation method of a semiconductor device, includes providing one or more memory elements each including a first semiconductor layer, second and third semiconductor layers, a dielectric film and a conductive film, a first electrode, a second electrode, and a third electrode, and performing operation of writing information on a memory element to be driven of the one or more memory elements. The operation of writing is performed by forming a filament in a region between the second and third semiconductor layers, which is a conductive path electrically linking these semiconductor layers, the filament being formed by causing a dielectric breakdown of at least a part of the dielectric film, through application of a voltage equal to or higher than a predetermined threshold between the second and third electrodes, thereby causing an electric current to flow between the conductive film and the third semiconductor layer.
    Type: Application
    Filed: February 14, 2012
    Publication date: August 23, 2012
    Applicant: SONY CORPORATION
    Inventors: Shigeru Kanematsu, Yuki Yanagisawa, Matsuo Iwasaki
  • Patent number: 8236746
    Abstract: A detergent composition containing: (a) a nonionic surfactant containing a polyoxyalkylene alkyl ether of which alkylene oxide moiety has an average number of moles of from 4 to 8; (b) an anionic surfactant, excluding a fatty acid and a salt thereof; and (c) a clay mineral represented by the general formula (I): [Si8(MgaAlb)O20(OH)4]X?·MeX+??(I) wherein a, b and x satisfy 0<a?6, 0<b?4, and x=12?2a?3b, and Me is at least one member selected from Na, K, Li, Ca, Mg and NH4, wherein the clay mineral is contained in an amount of 3% by weight or more, wherein a weight ratio of the component (a) to the component (b), (a)/(b), exceeds 1 and is less than 5.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: August 7, 2012
    Assignee: Kao Corporation
    Inventors: Yuki Yanagisawa, Kuniaki Mitsuyoshi, Wataru Ueno, Isao Yamada, Teruo Kubota
  • Publication number: 20100041578
    Abstract: A detergent composition containing: (a) a nonionic surfactant containing a polyoxyalkylene alkyl ether of which alkylene oxide moiety has an average number of moles of from 4 to 8; (b) an anionic surfactant, excluding a fatty acid and a salt thereof; and (c) a clay mineral represented by the general formula (I): [Si8(MgaAlb)O20(OH)4]X?.MeX+??(I) wherein a, b and x satisfy 0<a?6, 0<b?4, and x=12?2a?3, and Me is at least one member selected from Na, K, Li, Ca, Mg and NH4, wherein the clay mineral is contained in an amount of 3% by weight or more, wherein a weight ratio of the component (a) to the component (b), (a)/(b), exceeds 1 and is less than 5.
    Type: Application
    Filed: January 30, 2008
    Publication date: February 18, 2010
    Inventors: Yuki Yanagisawa, Kuniaki Mitsuyoshi, Wataru Ueno, Isao Yamada, Teruo Kubota
  • Publication number: 20070161538
    Abstract: A method of improving smoothness of an item to be washed during washing, including the step of washing the item with a washing liquid under conditions where an organic polymer having spinnability is present in the washing liquid; a process for hand-washing including the step of hand-washing an item to be washed with a washing liquid showing spinnability containing an organic polymer having spinnability, or a washing liquid prepared by diluting the washing liquid with more than 1-fold to 1,000-fold amount of water; a detergent composition containing an organic polymer having spinnability having an average molecular weight of 1,500,000 or more in an amount exceeding 0.1% by weight of the detergent composition; a laundry detergent composition comprising a polymer having an average molecular weight of 500,000 or more, wherein 60% by mole or more of constituting monomers has a sulfonic acid group or a salt form thereof, or a sulfuric acid group or a salt form thereof.
    Type: Application
    Filed: February 10, 2005
    Publication date: July 12, 2007
    Applicant: Kao Corporation
    Inventors: Yuki Yanagisawa, Katsuhiko Kasai, Yoshinobu Imaizumi, Hiroaki Warita, Kazuo Oki, Osamu Takiguchi, Takuya Masuda, Shu Yamaguchi