Patents by Inventor Yukie Nishikawa

Yukie Nishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7968933
    Abstract: A nonvolatile semiconductor memory device includes a tunnel insulating film, a floating gate electrode, an inter-electrode insulating film, and a control gate electrode. The tunnel insulating film is formed on a selected part of a surface of a semiconductor substrate. The floating gate electrode is formed on the tunnel insulating film. At least that interface region of the floating gate electrode, which is opposite to the substrate, is made of n-type Si or metal-based conductive material. The inter-electrode insulating film is formed on the floating gate electrode and made of high-permittivity material. The control gate electrode is formed on the inter-electrode insulating film. At least that interface region of the control gate electrode, which is on the side of the inter-electrode insulating film, is made of a p-type semiconductor layer containing at least one of Si and Ge.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: June 28, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shoko Kikuchi, Naoki Yasuda, Koichi Muraoka, Yukie Nishikawa, Hirotaka Nishino
  • Patent number: 7902588
    Abstract: A nonvolatile semiconductor memory device includes: a tunneling insulating film; a floating gate electrode; an inter-electrode insulating film, in which an interface facing the floating gate electrode and an interface facing a control gate electrode are defined as the first interface and the second interface, respectively; and a control gate electrode. The inter-electrode insulating film includes one or more first elements selected from rare earth elements, one or more second elements selected from Al, Ti, Zr, Hf, Ta, Mg, Ca, Sr and Ba, and oxygen. A composition ratio of the first element, which is defined as the number of atoms of the first element divided by that of the second element, is changed between the first interface and the second interface, and the composition ratio in the vicinity of the first interface is lower than that in the vicinity of the second interface.
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: March 8, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukie Nishikawa, Akira Takashima, Koichi Muraoka
  • Patent number: 7756736
    Abstract: A server (10) enables users (A-B) sharing the same working machine (1) to mutually monitor a usage state by each user. The server (10) receives a user ID, the working time, the engine cooling water temperature, and the current position that are detected in the working machine (1) through a satellite communication network, and calculates the usage time, the usage location, the load amount, and a usage proportion for each user. The server (10) sends a warning to the user terminals 20 when the usage time or location is not as planned, or the load amount is excessive. The server (10) periodically reports the usage times and locations, the load amounts, and the usage proportions for the users (A-B) to the user terminals (20). The server (10) allocates maintenance costs of the working machine (1) automatically between the users (A-B) according to the usage proportions of the users (A-B).
    Type: Grant
    Filed: October 26, 2004
    Date of Patent: July 13, 2010
    Assignee: Komatsu Ltd
    Inventors: Tetsuya Nakayama, Shuji Arakawa, Yukie Nishikawa, Hidenori Koizumi
  • Patent number: 7755136
    Abstract: A memory cell in a nonvolatile semiconductor memory device includes a tunneling insulating film, a floating gate electrode made of a Si containing conductive material, an inter-electrode insulating film made of rare-earth oxide, rare-earth nitride or rare-earth oxynitride, a control gate electrode, and a metal silicide film formed between the floating gate electrode and the inter-electrode insulating film.
    Type: Grant
    Filed: March 12, 2007
    Date of Patent: July 13, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukie Nishikawa, Akira Takashima, Tatsuo Shimizu
  • Publication number: 20090236653
    Abstract: A nonvolatile semiconductor memory device includes a tunnel insulating film, a floating gate electrode, an inter-electrode insulating film, and a control gate electrode. The tunnel insulating film is formed on a selected part of a surface of a semiconductor substrate. The floating gate electrode is formed on the tunnel insulating film. At least that interface region of the floating gate electrode, which is opposite to the substrate, is made of n-type Si or metal-based conductive material. The inter-electrode insulating film is formed on the floating gate electrode and made of high-permittivity material. The control gate electrode is formed on the inter-electrode insulating film. At least that interface region of the control gate electrode, which is on the side of the inter-electrode insulating film, is made of a p-type semiconductor layer containing at least one of Si and Ge.
    Type: Application
    Filed: May 27, 2009
    Publication date: September 24, 2009
    Inventors: Shoko Kikuchi, Naoki Yasuda, Koichi Muraoka, Yukie Nishikawa, Hirotaka Nishino
  • Patent number: 7560767
    Abstract: A nonvolatile semiconductor memory device according to an example of the present invention includes source/drain diffusion layers, a first insulation film on a channel between the source/drain diffusion layers, a floating gate electrode on the first insulation film and composed of first electrically conductive layers, a second insulation film on the floating gate electrode, and a control gate electrode on the second insulation film. In the case where one first electrically conductive layer excluding a top layer is defined as a reference layer among first electrically conductive layers, a work function of the reference layer is 4.0 eV or more and work functions of the reference layer and of the first electrically conductive layers above the reference layer gradually increase as the layers are proximal to the second insulation film.
    Type: Grant
    Filed: October 12, 2006
    Date of Patent: July 14, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoki Yasuda, Yukie Nishikawa, Koichi Muraoka
  • Patent number: 7550801
    Abstract: A nonvolatile semiconductor memory device includes a tunnel insulating film, a floating gate electrode, an inter-electrode insulating film, and a control gate electrode. The tunnel insulating film is formed on a selected part of a surface of a semiconductor substrate. The floating gate electrode is formed on the tunnel insulating film. At least that interface region of the floating gate electrode, which is opposite to the substrate, is made of n-type Si or metal-based conductive material. The inter-electrode insulating film is formed on the floating gate electrode and made of high-permittivity material. The control gate electrode is formed on the inter-electrode insulating film. At least that interface region of the control gate electrode, which is on the side of the inter-electrode insulating film, is made of a p-type semiconductor layer containing at least one of Si and Ge.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: June 23, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shoko Kikuchi, Naoki Yasuda, Koichi Muraoka, Yukie Nishikawa, Hirotaka Nishino
  • Patent number: 7538013
    Abstract: There is provided a field effect transistor including: a first insulating film formed on a semiconductor substrate, and including at least a metal oxide having a crystallinity and different in a lattice distance of a crystal on an interface from the semiconductor substrate; a channel region formed above the first insulating film, and different in the lattice distance from the semiconductor substrate; a source region and a drain region formed above the first insulating film on side surfaces of the channel region, respectively; a second insulating film formed right above the channel region; a gate insulating film formed on a side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain regions are formed; and a gate electrode formed through the gate insulating film on at least the side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain region are formed.
    Type: Grant
    Filed: June 22, 2006
    Date of Patent: May 26, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Matsushita, Yukie Nishikawa, Hideki Satake, Noburu Fukushima
  • Publication number: 20090014734
    Abstract: A semiconductor light emitting device includes an active layer, an electrode formed above the active layer, a current spreading layer formed between the active layer and the electrode, having n-type conductivity, having a larger bandgap energy than the active layer, and spreading electrons injected from the electrode in the plane of the active layer, and a surface processed layer formed on the current spreading layer, having a larger bandgap energy than the active layer, and having an uneven surface region with a large number of concave-convex structures. The electrode is not formed on the uneven surface region. The conduction band edge energy from the Fermi level of the surface processed layer is higher than that of the current spreading layer.
    Type: Application
    Filed: July 11, 2008
    Publication date: January 15, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yukie Nishikawa, Shinji Nunotani
  • Publication number: 20090011537
    Abstract: The present invention is to obtain an MIS transistor which allows considerable reduction in threshold fluctuation for each transistor and has a low threshold voltage. First gate electrode material for nMIS and second gate electrode material for pMIS can be mutually converted to each other, so that a process can be simplified. Such a fact that a dependency of a work function on a doping amount is small is first disclosed, so that fluctuation in threshold voltage for each transistor hardly occurs.
    Type: Application
    Filed: June 26, 2008
    Publication date: January 8, 2009
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Takeshi Yamaguchi, Yukie Nishikawa
  • Patent number: 7405451
    Abstract: The present invention is to obtain an MIS transistor which allows considerable reduction in threshold fluctuation for each transistor and has a low threshold voltage. First gate electrode material for nMIS and second gate electrode material for pMIS can be mutually converted to each other, so that a process can be simplified. Such a fact that a dependency of a work function on a doping amount is small is first disclosed, so that fluctuation in threshold voltage for each transistor hardly occurs.
    Type: Grant
    Filed: December 27, 2004
    Date of Patent: July 29, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Takeshi Yamaguchi, Yukie Nishikawa
  • Publication number: 20080121979
    Abstract: A nonvolatile semiconductor memory device includes: a tunneling insulating film; a floating gate electrode; an inter-electrode insulating film, in which an interface facing the floating gate electrode and an interface facing a control gate electrode are defined as the first interface and the second interface, respectively; and a control gate electrode. The inter-electrode insulating film includes one or more first elements selected from rare earth elements, one or more second elements selected from Al, Ti, Zr, Hf, Ta, Mg, Ca, Sr and Ba, and oxygen. A composition ratio of the first element, which is defined as the number of atoms of the first element divided by that of the second element, is changed between the first interface and the second interface, and the composition ratio in the vicinity of the first interface is lower than that in the vicinity of the second interface.
    Type: Application
    Filed: August 28, 2007
    Publication date: May 29, 2008
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yukie NISHIKAWA, Akira Takashima, Koichi Muraoka
  • Publication number: 20070284646
    Abstract: According to an aspect of the invention, a nonvolatile semiconductor memory device includes: a semiconductor layer comprising an n-type semiconductor region; p-type source-drain regions separated from each other within the n-type semiconductor region; a charge storage layer provided on the semiconductor layer and between the p-type source-drain regions, the charge storage layer comprising a high dielectric constant material; and a control gate electrode provided on the charge storage layer and comprising a material selected from n-type Si, a metal-based conductive material, and a p-type semiconductor material including at least one of Si and Ge.
    Type: Application
    Filed: March 23, 2007
    Publication date: December 13, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Shoko Kikuchi, Naoki Yasuda, Koichi Muraoka, Yukie Nishikawa, Hirotaka Nishino
  • Publication number: 20070215924
    Abstract: A memory cell in a nonvolatile semiconductor memory device includes a tunneling insulating film, a floating gate electrode made of a Si containing conductive material, an inter-electrode insulating film made of rare-earth oxide, rare-earth nitride or rare-earth oxynitride, a control gate electrode, and a metal silicide film formed between the floating gate electrode and the inter-electrode insulating film.
    Type: Application
    Filed: March 12, 2007
    Publication date: September 20, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yukie Nishikawa, Akira Takashima, Tatsuo Shimizu
  • Publication number: 20070132004
    Abstract: A nonvolatile semiconductor memory device according to an example of the present invention includes source/drain diffusion layers, a first insulation film on a channel between the source/drain diffusion layers, a floating gate electrode on the first insulation film and composed of first electrically conductive layers, a second insulation film on the floating gate electrode, and a control gate electrode on the second insulation film. In the case where one first electrically conductive layer excluding a top layer is defined as a reference layer among first electrically conductive layers, a work function of the reference layer is 4.0 eV or more and work functions of the reference layer and of the first electrically conductive layers above the reference layer gradually increase as the layers are proximal to the second insulation film.
    Type: Application
    Filed: October 12, 2006
    Publication date: June 14, 2007
    Inventors: Naoki YASUDA, Yukie NISHIKAWA, Koichi MURAOKA
  • Publication number: 20070094055
    Abstract: A server (10) enables users (A-B) sharing the same working machine (1) to mutually monitor a usage state by each user. The server (10) receives a user ID, the working time, the engine cooling water temperature, and the current position that are detected in the working machine (1) through a satellite communication network, and calculates the usage time, the usage location, the load amount, and a usage proportion for each user. The server (10) sends a warning to the user terminals 20 when the usage time or location is not as planned, or the load amount is excessive. The server (10) periodically reports the usage times and locations, the load amounts, and the usage proportions for the users (A-B) to the user terminals (20). The server (10) allocates maintenance costs of the working machine (1) automatically between the users (A-B) according to the usage proportions of the users (A-B).
    Type: Application
    Filed: October 26, 2004
    Publication date: April 26, 2007
    Applicant: KOMATSU LTD.
    Inventors: Tetsuya Nakayama, Shuji Arakawa, Yukie Nishikawa, Hidenori Koizumi
  • Publication number: 20070042547
    Abstract: A nonvolatile semiconductor memory device includes a tunnel insulating film, a floating gate electrode, an inter-electrode insulating film, and a control gate electrode. The tunnel insulating film is formed on a selected part of a surface of a semiconductor substrate. The floating gate electrode is formed on the tunnel insulating film. At least that interface region of the floating gate electrode, which is opposite to the substrate, is made of n-type Si or metal-based conductive material. The inter-electrode insulating film is formed on the floating gate electrode and made of high-permittivity material. The control gate electrode is formed on the inter-electrode insulating film. At least that interface region of the control gate electrode, which is on the side of the inter-electrode insulating film, is made of a p-type semiconductor layer containing at least one of Si and Ge.
    Type: Application
    Filed: May 15, 2006
    Publication date: February 22, 2007
    Inventors: Shoko Kikuchi, Naoki Yasuda, Koichi Muraoka, Yukie Nishikawa, Hirotaka Nishino
  • Publication number: 20060237837
    Abstract: There is provided a field effect transistor including: a first insulating film formed on a semiconductor substrate, and including at least a metal oxide having a crystallinity and different in a lattice distance of a crystal on an interface from the semiconductor substrate; a convex channel region formed above the first insulating film, and different in the lattice distance from the semiconductor substrate; a source region and a drain region formed above the first insulating film on side surfaces of the channel region, respectively; a second insulating film formed right above the channel region; a gate insulating film formed on a side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain regions are formed; and a gate electrode formed through the gate insulating film on at least the side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain region are formed.
    Type: Application
    Filed: June 22, 2006
    Publication date: October 26, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Matsushita, Yukie Nishikawa, Hideki Satake, Noburu Fukushima
  • Patent number: 7115953
    Abstract: A semiconductor device includes a semiconductor substrate containing Si as a main component, and an active element formed on the semiconductor substrate and including an insulating metal silicide thin film formed on the semiconductor substrate, dangling bonds of Si of the semiconductor substrate being terminated by the insulating metal silicide thin film.
    Type: Grant
    Filed: February 4, 2005
    Date of Patent: October 3, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Takeshi Yamaguchi, Yukie Nishikawa
  • Patent number: 7091561
    Abstract: There is provided a field effect transistor including: a first insulating film formed on a semiconductor substrate, and including at least a metal oxide having a crystallinity and different in a lattice distance of a crystal on an interface from the semiconductor substrate; a convex channel region formed above the first insulating film, and different in the lattice distance from the semiconductor substrate; a source region and a drain region formed above the first insulating film on side surfaces of the channel region, respectively; a second insulating film formed right above the channel region; a gate insulating film formed on a side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain regions are formed; and a gate electrode formed through the gate insulating film on at least the side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain region are formed.
    Type: Grant
    Filed: June 9, 2004
    Date of Patent: August 15, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Matsushita, Yukie Nishikawa, Hideki Satake, Noburu Fukushima