Patents by Inventor Yukie Nishikawa
Yukie Nishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7968933Abstract: A nonvolatile semiconductor memory device includes a tunnel insulating film, a floating gate electrode, an inter-electrode insulating film, and a control gate electrode. The tunnel insulating film is formed on a selected part of a surface of a semiconductor substrate. The floating gate electrode is formed on the tunnel insulating film. At least that interface region of the floating gate electrode, which is opposite to the substrate, is made of n-type Si or metal-based conductive material. The inter-electrode insulating film is formed on the floating gate electrode and made of high-permittivity material. The control gate electrode is formed on the inter-electrode insulating film. At least that interface region of the control gate electrode, which is on the side of the inter-electrode insulating film, is made of a p-type semiconductor layer containing at least one of Si and Ge.Type: GrantFiled: May 27, 2009Date of Patent: June 28, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Shoko Kikuchi, Naoki Yasuda, Koichi Muraoka, Yukie Nishikawa, Hirotaka Nishino
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Patent number: 7902588Abstract: A nonvolatile semiconductor memory device includes: a tunneling insulating film; a floating gate electrode; an inter-electrode insulating film, in which an interface facing the floating gate electrode and an interface facing a control gate electrode are defined as the first interface and the second interface, respectively; and a control gate electrode. The inter-electrode insulating film includes one or more first elements selected from rare earth elements, one or more second elements selected from Al, Ti, Zr, Hf, Ta, Mg, Ca, Sr and Ba, and oxygen. A composition ratio of the first element, which is defined as the number of atoms of the first element divided by that of the second element, is changed between the first interface and the second interface, and the composition ratio in the vicinity of the first interface is lower than that in the vicinity of the second interface.Type: GrantFiled: August 28, 2007Date of Patent: March 8, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yukie Nishikawa, Akira Takashima, Koichi Muraoka
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Patent number: 7756736Abstract: A server (10) enables users (A-B) sharing the same working machine (1) to mutually monitor a usage state by each user. The server (10) receives a user ID, the working time, the engine cooling water temperature, and the current position that are detected in the working machine (1) through a satellite communication network, and calculates the usage time, the usage location, the load amount, and a usage proportion for each user. The server (10) sends a warning to the user terminals 20 when the usage time or location is not as planned, or the load amount is excessive. The server (10) periodically reports the usage times and locations, the load amounts, and the usage proportions for the users (A-B) to the user terminals (20). The server (10) allocates maintenance costs of the working machine (1) automatically between the users (A-B) according to the usage proportions of the users (A-B).Type: GrantFiled: October 26, 2004Date of Patent: July 13, 2010Assignee: Komatsu LtdInventors: Tetsuya Nakayama, Shuji Arakawa, Yukie Nishikawa, Hidenori Koizumi
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Patent number: 7755136Abstract: A memory cell in a nonvolatile semiconductor memory device includes a tunneling insulating film, a floating gate electrode made of a Si containing conductive material, an inter-electrode insulating film made of rare-earth oxide, rare-earth nitride or rare-earth oxynitride, a control gate electrode, and a metal silicide film formed between the floating gate electrode and the inter-electrode insulating film.Type: GrantFiled: March 12, 2007Date of Patent: July 13, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Yukie Nishikawa, Akira Takashima, Tatsuo Shimizu
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Publication number: 20090236653Abstract: A nonvolatile semiconductor memory device includes a tunnel insulating film, a floating gate electrode, an inter-electrode insulating film, and a control gate electrode. The tunnel insulating film is formed on a selected part of a surface of a semiconductor substrate. The floating gate electrode is formed on the tunnel insulating film. At least that interface region of the floating gate electrode, which is opposite to the substrate, is made of n-type Si or metal-based conductive material. The inter-electrode insulating film is formed on the floating gate electrode and made of high-permittivity material. The control gate electrode is formed on the inter-electrode insulating film. At least that interface region of the control gate electrode, which is on the side of the inter-electrode insulating film, is made of a p-type semiconductor layer containing at least one of Si and Ge.Type: ApplicationFiled: May 27, 2009Publication date: September 24, 2009Inventors: Shoko Kikuchi, Naoki Yasuda, Koichi Muraoka, Yukie Nishikawa, Hirotaka Nishino
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Patent number: 7560767Abstract: A nonvolatile semiconductor memory device according to an example of the present invention includes source/drain diffusion layers, a first insulation film on a channel between the source/drain diffusion layers, a floating gate electrode on the first insulation film and composed of first electrically conductive layers, a second insulation film on the floating gate electrode, and a control gate electrode on the second insulation film. In the case where one first electrically conductive layer excluding a top layer is defined as a reference layer among first electrically conductive layers, a work function of the reference layer is 4.0 eV or more and work functions of the reference layer and of the first electrically conductive layers above the reference layer gradually increase as the layers are proximal to the second insulation film.Type: GrantFiled: October 12, 2006Date of Patent: July 14, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Naoki Yasuda, Yukie Nishikawa, Koichi Muraoka
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Patent number: 7550801Abstract: A nonvolatile semiconductor memory device includes a tunnel insulating film, a floating gate electrode, an inter-electrode insulating film, and a control gate electrode. The tunnel insulating film is formed on a selected part of a surface of a semiconductor substrate. The floating gate electrode is formed on the tunnel insulating film. At least that interface region of the floating gate electrode, which is opposite to the substrate, is made of n-type Si or metal-based conductive material. The inter-electrode insulating film is formed on the floating gate electrode and made of high-permittivity material. The control gate electrode is formed on the inter-electrode insulating film. At least that interface region of the control gate electrode, which is on the side of the inter-electrode insulating film, is made of a p-type semiconductor layer containing at least one of Si and Ge.Type: GrantFiled: May 15, 2006Date of Patent: June 23, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Shoko Kikuchi, Naoki Yasuda, Koichi Muraoka, Yukie Nishikawa, Hirotaka Nishino
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Patent number: 7538013Abstract: There is provided a field effect transistor including: a first insulating film formed on a semiconductor substrate, and including at least a metal oxide having a crystallinity and different in a lattice distance of a crystal on an interface from the semiconductor substrate; a channel region formed above the first insulating film, and different in the lattice distance from the semiconductor substrate; a source region and a drain region formed above the first insulating film on side surfaces of the channel region, respectively; a second insulating film formed right above the channel region; a gate insulating film formed on a side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain regions are formed; and a gate electrode formed through the gate insulating film on at least the side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain region are formed.Type: GrantFiled: June 22, 2006Date of Patent: May 26, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Daisuke Matsushita, Yukie Nishikawa, Hideki Satake, Noburu Fukushima
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Publication number: 20090014734Abstract: A semiconductor light emitting device includes an active layer, an electrode formed above the active layer, a current spreading layer formed between the active layer and the electrode, having n-type conductivity, having a larger bandgap energy than the active layer, and spreading electrons injected from the electrode in the plane of the active layer, and a surface processed layer formed on the current spreading layer, having a larger bandgap energy than the active layer, and having an uneven surface region with a large number of concave-convex structures. The electrode is not formed on the uneven surface region. The conduction band edge energy from the Fermi level of the surface processed layer is higher than that of the current spreading layer.Type: ApplicationFiled: July 11, 2008Publication date: January 15, 2009Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yukie Nishikawa, Shinji Nunotani
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Publication number: 20090011537Abstract: The present invention is to obtain an MIS transistor which allows considerable reduction in threshold fluctuation for each transistor and has a low threshold voltage. First gate electrode material for nMIS and second gate electrode material for pMIS can be mutually converted to each other, so that a process can be simplified. Such a fact that a dependency of a work function on a doping amount is small is first disclosed, so that fluctuation in threshold voltage for each transistor hardly occurs.Type: ApplicationFiled: June 26, 2008Publication date: January 8, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Tatsuo Shimizu, Takeshi Yamaguchi, Yukie Nishikawa
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Patent number: 7405451Abstract: The present invention is to obtain an MIS transistor which allows considerable reduction in threshold fluctuation for each transistor and has a low threshold voltage. First gate electrode material for nMIS and second gate electrode material for pMIS can be mutually converted to each other, so that a process can be simplified. Such a fact that a dependency of a work function on a doping amount is small is first disclosed, so that fluctuation in threshold voltage for each transistor hardly occurs.Type: GrantFiled: December 27, 2004Date of Patent: July 29, 2008Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuo Shimizu, Takeshi Yamaguchi, Yukie Nishikawa
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Publication number: 20080121979Abstract: A nonvolatile semiconductor memory device includes: a tunneling insulating film; a floating gate electrode; an inter-electrode insulating film, in which an interface facing the floating gate electrode and an interface facing a control gate electrode are defined as the first interface and the second interface, respectively; and a control gate electrode. The inter-electrode insulating film includes one or more first elements selected from rare earth elements, one or more second elements selected from Al, Ti, Zr, Hf, Ta, Mg, Ca, Sr and Ba, and oxygen. A composition ratio of the first element, which is defined as the number of atoms of the first element divided by that of the second element, is changed between the first interface and the second interface, and the composition ratio in the vicinity of the first interface is lower than that in the vicinity of the second interface.Type: ApplicationFiled: August 28, 2007Publication date: May 29, 2008Applicant: Kabushiki Kaisha ToshibaInventors: Yukie NISHIKAWA, Akira Takashima, Koichi Muraoka
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Publication number: 20070284646Abstract: According to an aspect of the invention, a nonvolatile semiconductor memory device includes: a semiconductor layer comprising an n-type semiconductor region; p-type source-drain regions separated from each other within the n-type semiconductor region; a charge storage layer provided on the semiconductor layer and between the p-type source-drain regions, the charge storage layer comprising a high dielectric constant material; and a control gate electrode provided on the charge storage layer and comprising a material selected from n-type Si, a metal-based conductive material, and a p-type semiconductor material including at least one of Si and Ge.Type: ApplicationFiled: March 23, 2007Publication date: December 13, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shoko Kikuchi, Naoki Yasuda, Koichi Muraoka, Yukie Nishikawa, Hirotaka Nishino
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Publication number: 20070215924Abstract: A memory cell in a nonvolatile semiconductor memory device includes a tunneling insulating film, a floating gate electrode made of a Si containing conductive material, an inter-electrode insulating film made of rare-earth oxide, rare-earth nitride or rare-earth oxynitride, a control gate electrode, and a metal silicide film formed between the floating gate electrode and the inter-electrode insulating film.Type: ApplicationFiled: March 12, 2007Publication date: September 20, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yukie Nishikawa, Akira Takashima, Tatsuo Shimizu
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Publication number: 20070132004Abstract: A nonvolatile semiconductor memory device according to an example of the present invention includes source/drain diffusion layers, a first insulation film on a channel between the source/drain diffusion layers, a floating gate electrode on the first insulation film and composed of first electrically conductive layers, a second insulation film on the floating gate electrode, and a control gate electrode on the second insulation film. In the case where one first electrically conductive layer excluding a top layer is defined as a reference layer among first electrically conductive layers, a work function of the reference layer is 4.0 eV or more and work functions of the reference layer and of the first electrically conductive layers above the reference layer gradually increase as the layers are proximal to the second insulation film.Type: ApplicationFiled: October 12, 2006Publication date: June 14, 2007Inventors: Naoki YASUDA, Yukie NISHIKAWA, Koichi MURAOKA
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Publication number: 20070094055Abstract: A server (10) enables users (A-B) sharing the same working machine (1) to mutually monitor a usage state by each user. The server (10) receives a user ID, the working time, the engine cooling water temperature, and the current position that are detected in the working machine (1) through a satellite communication network, and calculates the usage time, the usage location, the load amount, and a usage proportion for each user. The server (10) sends a warning to the user terminals 20 when the usage time or location is not as planned, or the load amount is excessive. The server (10) periodically reports the usage times and locations, the load amounts, and the usage proportions for the users (A-B) to the user terminals (20). The server (10) allocates maintenance costs of the working machine (1) automatically between the users (A-B) according to the usage proportions of the users (A-B).Type: ApplicationFiled: October 26, 2004Publication date: April 26, 2007Applicant: KOMATSU LTD.Inventors: Tetsuya Nakayama, Shuji Arakawa, Yukie Nishikawa, Hidenori Koizumi
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Publication number: 20070042547Abstract: A nonvolatile semiconductor memory device includes a tunnel insulating film, a floating gate electrode, an inter-electrode insulating film, and a control gate electrode. The tunnel insulating film is formed on a selected part of a surface of a semiconductor substrate. The floating gate electrode is formed on the tunnel insulating film. At least that interface region of the floating gate electrode, which is opposite to the substrate, is made of n-type Si or metal-based conductive material. The inter-electrode insulating film is formed on the floating gate electrode and made of high-permittivity material. The control gate electrode is formed on the inter-electrode insulating film. At least that interface region of the control gate electrode, which is on the side of the inter-electrode insulating film, is made of a p-type semiconductor layer containing at least one of Si and Ge.Type: ApplicationFiled: May 15, 2006Publication date: February 22, 2007Inventors: Shoko Kikuchi, Naoki Yasuda, Koichi Muraoka, Yukie Nishikawa, Hirotaka Nishino
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Publication number: 20060237837Abstract: There is provided a field effect transistor including: a first insulating film formed on a semiconductor substrate, and including at least a metal oxide having a crystallinity and different in a lattice distance of a crystal on an interface from the semiconductor substrate; a convex channel region formed above the first insulating film, and different in the lattice distance from the semiconductor substrate; a source region and a drain region formed above the first insulating film on side surfaces of the channel region, respectively; a second insulating film formed right above the channel region; a gate insulating film formed on a side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain regions are formed; and a gate electrode formed through the gate insulating film on at least the side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain region are formed.Type: ApplicationFiled: June 22, 2006Publication date: October 26, 2006Applicant: Kabushiki Kaisha ToshibaInventors: Daisuke Matsushita, Yukie Nishikawa, Hideki Satake, Noburu Fukushima
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Patent number: 7115953Abstract: A semiconductor device includes a semiconductor substrate containing Si as a main component, and an active element formed on the semiconductor substrate and including an insulating metal silicide thin film formed on the semiconductor substrate, dangling bonds of Si of the semiconductor substrate being terminated by the insulating metal silicide thin film.Type: GrantFiled: February 4, 2005Date of Patent: October 3, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuo Shimizu, Takeshi Yamaguchi, Yukie Nishikawa
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Patent number: 7091561Abstract: There is provided a field effect transistor including: a first insulating film formed on a semiconductor substrate, and including at least a metal oxide having a crystallinity and different in a lattice distance of a crystal on an interface from the semiconductor substrate; a convex channel region formed above the first insulating film, and different in the lattice distance from the semiconductor substrate; a source region and a drain region formed above the first insulating film on side surfaces of the channel region, respectively; a second insulating film formed right above the channel region; a gate insulating film formed on a side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain regions are formed; and a gate electrode formed through the gate insulating film on at least the side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain region are formed.Type: GrantFiled: June 9, 2004Date of Patent: August 15, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Daisuke Matsushita, Yukie Nishikawa, Hideki Satake, Noburu Fukushima