Patents by Inventor Yukie Nishikawa
Yukie Nishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7015121Abstract: A method of manufacturing a semiconductor device comprises a step of depositing a crystalline insulating layer oriented in a predetermined crystal face orientation by epitaxial growth on an amorphous semiconductor layer, a step of depositing a second amorphous semiconductor layer on the crystalline insulating layer, a step of growing said first and second semiconductor layers into a polycrystal or single crystal layer in a solid phase, using said crystalline insulating film as core, and a step of forming a functional element containing said first and second semiconductor layer.Type: GrantFiled: August 4, 2004Date of Patent: March 21, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Yuichiro Mitani, Yukie Nishikawa
-
Publication number: 20050230759Abstract: A semiconductor device includes a semiconductor substrate containing Si as a main component, and an active element formed on the semiconductor substrate and including an insulating metal silicide thin film formed on the semiconductor substrate, dangling bonds of Si of the semiconductor substrate being terminated by the insulating metal silicide thin film.Type: ApplicationFiled: February 4, 2005Publication date: October 20, 2005Inventors: Tatsuo Shimizu, Takeshi Yamaguchi, Yukie Nishikawa
-
Patent number: 6914312Abstract: A MIS type field effect transistor including gate dielectrics having a rare-earth metal oxynitride layer with a high dielectric constant, which can maintain good interface characteristics, can be provided. A field effect transistor according to one aspect of this invention includes a gate dielectric having a substantially crystalline rare-earth metal oxynitride layer containing one or more metals selected from rare-earth metals, oxygen, and nitrogen. The rare-earth metal oxynitride layer contacts a predetermined region of a Si semiconductor substrate, and the nitrogen exists at the interface between the rare-earth metal oxynitride layer and the Si semiconductor substrate, and in the bulk of the rare-earth metal oxynitride. The transistor further includes a gate electrode formed on the gate dielectrics and source and drain regions, one being formed at one side of the gate electrode and the other being formed at the other side of the gate electrode in the Si semiconductor substrate.Type: GrantFiled: March 26, 2003Date of Patent: July 5, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Yukie Nishikawa, Noburu Fukushima, Takeshi Yamaguchi, Hideki Satake
-
Publication number: 20050139926Abstract: The present invention is to obtain an MIS transistor which allows considerable reduction in threshold fluctuation for each transistor and has a low threshold voltage. First gate electrode material for nMIS and second gate electrode material for pMIS can be mutually converted to each other, so that a process can be simplified. Such a fact that a dependency of a work function on a doping amount is small is first disclosed, so that fluctuation in threshold voltage for each transistor hardly occurs.Type: ApplicationFiled: December 27, 2004Publication date: June 30, 2005Inventors: Tatsuo Shimizu, Takeshi Yamaguchi, Yukie Nishikawa
-
Publication number: 20050017304Abstract: There is provided a field effect transistor including: a first insulating film formed on a semiconductor substrate, and including at least a metal oxide having a crystallinity and different in a lattice distance of a crystal on an interface from the semiconductor substrate; a convex channel region formed above the first insulating film, and different in the lattice distance from the semiconductor substrate; a source region and a drain region formed above the first insulating film on side surfaces of the channel region, respectively; a second insulating film formed right above the channel region; a gate insulating film formed on a side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain regions are formed; and a gate electrode formed through the gate insulating film on at least the side surface of the channel region different from the side surfaces of the channel region on which the source region and the drain region are formed.Type: ApplicationFiled: June 9, 2004Publication date: January 27, 2005Inventors: Daisuke Matsushita, Yukie Nishikawa, Hideki Satake, Noburu Fukushima
-
Publication number: 20050009306Abstract: A method of manufacturing a semiconductor device comprises a step of depositing a crystalline insulating layer oriented in a predetermined crystal face orientation by epitaxial growth on an amorphous semiconductor layer, a step of depositing a second amorphous semiconductor layer on the crystalline insulating layer, a step of growing said first and second semiconductor layers into a polycrystal or single crystal layer in a solid phase, using said crystalline insulating film as core, and a step of forming a functional element containing said first and second semiconductor layer.Type: ApplicationFiled: August 4, 2004Publication date: January 13, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yuichiro Mitani, Yukie Nishikawa
-
Patent number: 6787433Abstract: A method of manufacturing a semiconductor device comprises a step of depositing a crystalline insulating layer oriented in a predetermined crystal face orientation by epitaxial growth on an amorphous semiconductor layer, a step of depositing a second amorphous semiconductor layer on the crystalline insulating layer, a step of growing said first and second semiconductor layers into a polycrystal or single crystal layer in a solid phase, using said crystalline insulating film as core, and a step of forming a functional element containing said first and second semiconductor layer.Type: GrantFiled: September 19, 2002Date of Patent: September 7, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Yuichiro Mitani, Yukie Nishikawa
-
Publication number: 20030183885Abstract: A MIS type field effect transistor including gate dielectrics having a rare-earth metal oxynitride layer with a high dielectric constant, which can maintain good interface characteristics, can be provided. A field effect transistor according to one aspect of this invention includes a gate dielectric having a substantially crystalline rare-earth metal oxynitride layer containing one or more metals selected from rare-earth metals, oxygen, and nitrogen. The rare-earth metal oxynitride layer contacts a predetermined region of a Si semiconductor substrate, and the nitrogen exists at the interface between the rare-earth metal oxynitride layer and the Si semiconductor substrate, and in the bulk of the rare-earth metal oxynitride. The transistor further includes a gate electrode formed on the gate dielectrics and source and drain regions, one being formed at one side of the gate electrode and the other being formed at the other side of the gate electrode in the Si semiconductor substrate.Type: ApplicationFiled: March 26, 2003Publication date: October 2, 2003Applicant: Kabushiki Kaisha ToshibaInventors: Yukie Nishikawa, Noburu Fukushima, Takeshi Yamaguchi, Hideki Satake
-
Publication number: 20030057491Abstract: A method of manufacturing a semiconductor device comprises a step of depositing a crystalline insulating layer oriented in a predetermined crystal face orientation by epitaxial growth on an amorphous semiconductor layer, a step of depositing a second amorphous semiconductor layer on the crystalline insulating layer, a step of growing said first and second semiconductor layers into a polycrystal or single crystal layer in a solid phase, using said crystalline insulating film as core, and a step of forming a functional element containing said first and second semiconductor layer.Type: ApplicationFiled: September 19, 2002Publication date: March 27, 2003Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yuichiro Mitani, Yukie Nishikawa
-
Patent number: 6080599Abstract: The present invention is intended to provide a semiconductor optoelectric device with high luminescent efficiency and a method of manufacturing the same. The semiconductor optoelectric device 18 according to the present invention is constructed by depositing compound-semiconductor layers 13 and 14 on a monocrystalline substrate 11 of a hexagonal close-packed structure. The shape of the monocrystalline substrate 11 is a parallelogram. Individual sides of the parallelogram are parallel to a <11-20> orientation. As the monocrystalline substrate, sapphire, zinc oxide or silicon carbide may be used. As the compound-semiconductor layers, an n-type GaN layer 13 and p-type GaN layer 14 may be used.Type: GrantFiled: June 2, 1998Date of Patent: June 27, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Masahiro Yamamoto, Hidetoshi Fujimoto, Yoshihiro Kokubun, Masayuki Ishikawa, Shinji Saito, Yukie Nishikawa, John Rennie
-
Patent number: 6072203Abstract: In an HEMT, a channel forming layer is arranged above a semi-insulating substrate via a buffer layer. A spacer layer is arranged on the channel forming layer and an electron supplying layer and a Schottky contact layer are sequentially arranged on the spacer layer. A diffusion preventing layer, for preventing a metal element of a gate electrode from diffusing into the channel forming layer, is arranged in the Schottky contact layer.Type: GrantFiled: March 24, 1998Date of Patent: June 6, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Chiharu Nozaki, Minoru Amano, Yukie Nishikawa, Masayuki Sugiura, Takao Noda, Aki Sasaki, Yasuo Ashizawa
-
Patent number: 6005263Abstract: A semiconductor device includes a first semiconductor layer formed of first semiconductor, a second semiconductor layer formed on the first semiconductor layer and formed of second semiconductor of a group different from a group to which the first semiconductor belongs, and a third semiconductor layer formed between the first and second semiconductor layers, the third semiconductor layer being one of a layer formed of third semiconductor of the same group as the first semiconductor and having an impurity concentration higher than the first semiconductor layer and a layer formed of fourth semiconductor of the same group as the second semiconductor and having an impurity concentration higher than the second semiconductor layer.Type: GrantFiled: November 24, 1997Date of Patent: December 21, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Shinji Saito, Masaaki Onomura, Yukie Nishikawa, Masayuki Ishikawa, Peter James Parbrook
-
Patent number: 5864171Abstract: The present invention is intended to provide a semiconductor optoelectric device with high luminescent efficiency and a method of manufacturing the same. The semiconductor optoelectric device 18 according to the present invention is constructed by depositing compound-semiconductor layers 13 and 14 on a monocrystalline substrate 11 of a hexagonal close-packed structure. The shape of the monocrystalline substrate 11 is a parallelogram. Individual sides of the parallelogram are parallel to a <11-20> orientation. As the monocrystalline substrate, sapphire, zinc oxide or silicon carbide may be used. As the compound-semiconductor layers, an n-type GaN layer 13 and p-type GaN layer 14 may be used.Type: GrantFiled: March 29, 1996Date of Patent: January 26, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Masahiro Yamamoto, Hidetoshi Fujimoto, Yoshihiro Kokubun, Masayuki Ishikawa, Shinji Saito, Yukie Nishikawa, John Rennie
-
Patent number: 5821555Abstract: A semiconductor device includes a first semiconductor layer formed of first semiconductor, a second semiconductor layer formed on the first semiconductor layer and formed of second semiconductor of a group different from a group to which the first semiconductor belongs, and a third semiconductor layer formed between the first and second semiconductor layers, the third semiconductor layer being one of a layer formed of third semiconductor of the same group as the first semiconductor and having an impurity concentration higher than the first semiconductor layer and a layer formed of fourth semiconductor of the same group as the second semiconductor and having an impurity concentration higher than the second semiconductor layer.Type: GrantFiled: March 20, 1996Date of Patent: October 13, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Shinji Saito, Masaaki Onomura, Yukie Nishikawa, Masayuki Ishikawa, Peter James Parbrook
-
Patent number: 5696389Abstract: A light-emitting semiconductor device comprising an n-type cladding layer provided on a surface of a substrate and having concentric first and second parts, a first electrode mounted on the first part of the n-type cladding layer, a p-type cladding layer provided above the surface of the substrate and surrounding the first electrode and the second part of the n-type cladding layer, and a second electrode provided on the p-type cladding layer.Type: GrantFiled: March 13, 1995Date of Patent: December 9, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Ishikawa, Hideto Sugawara, Yukie Nishikawa, Masaaki Onomura, Shinji Saito, Peter James Parbrook, Genichi Hatakoshi, Koichi Nitta, John Rennie, Hiroaki Yoshida, Atsushi Kamata
-
Patent number: 5585649Abstract: A compound semiconductor device with an improved internal current blocking structure. The semiconductor device includes an n-clad layer of II-VI compound semiconductor, a p-clad layer of II-VI compound semiconductor, an active layer of II-VI compound semiconductor between the n-clad and p-clad layers, a very thin current blocking layer of n-type II-VI compound semiconductor on the p-clad layer and providing an opening, a p-contact layer of p-type II-VI compound semiconductor on the p-clad layer and the current blocking layer at the opening, and a p-side electrode on the p-contact layer.Type: GrantFiled: March 14, 1995Date of Patent: December 17, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Ishikawa, Yukie Nishikawa, Masaaki Onomura, Shinji Saito, Peter J. Parbrook, Genichi Hatakoshi
-
Patent number: 5488233Abstract: This invention provides a semiconductor light-emitting device including a semiconductor substrate consisting of a compound semiconductor of elements in the third and fifth groups of the period table, a first compound semiconductor layer formed directly on at least a portion of the semiconductor substrate and consisting of a compound semiconductor containing at least In and P, and a second compound semiconductor formed directly on the first compound semiconductor layer and consisting of a compound semiconductor of elements in the second and sixth groups of the periodic table. With this arrangement, it is possible to sufficiently prevent the occurrence of defects in the interface between the semiconductor substrate and the second compound semiconductor layer consisting of the compound semiconductor of the elements in the second and sixth groups of the periodic table.Type: GrantFiled: March 11, 1994Date of Patent: January 30, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Ishikawa, Yukie Nishikawa, Shinji Saito, Peter J. Parbrook, Masaaki Onomura, Koichi Nitta, Genichi Hatakoshi
-
Patent number: 5321712Abstract: A semiconductor light-emitting element includes a semiconductor substrate of a first conductivity type, a lower cladding layer formed on the semiconductor substrate and constituted by an InGaAlP-based compound of the first conductivity type, an active layer formed on the lower cladding layer, and constituted by a material selected from the group consisting of GaAs, GaAlAs, and InGaAs, and an upper cladding layer formed on the active layer, and constituted by the InGaAlP-based compound of a second conductivity type, wherein the InGaAlP-based compound is represented by a formula In.sub.y (Ga.sub.1-x Al.sub.x).sub.y P, where x is in the range of 0.3 to 0.7 and y is in the range of 0.45 to 0.55.Type: GrantFiled: January 29, 1993Date of Patent: June 14, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhiko Itaya, Koichi Nitta, Genichi Hatakoshi, Yukie Nishikawa, Hideto Sugawara, Mariko Suzuki
-
Patent number: 5305341Abstract: According to this invention, in a semiconductor laser, an n-type InGaAlP cladding layer, an InGaP active layer, and a p-type InGaAlP cladding layer are sequentially grown on an n-type GaAs substrate to form a double hetero structure. The active layer is constituted by an ordered structure having regularity in the <111> directions, and the p-type cladding layer is constituted by a disordered structure. Band discontinuity in conduction band between the active layer and the p-type cladding layer is increased to improve the temperature characteristics of the laser.Type: GrantFiled: February 19, 1992Date of Patent: April 19, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Yukie Nishikawa, Koichi Nitta, Genichi Hatakoshi, Masaki Okajima, Minoru Watanabe, Kazuhiko Itaya
-
Patent number: 5282218Abstract: A semiconductor laser device for radiating a laser beam from a double heterostructure section in which injected carriers having an energy source of the laser beam are confined consists of a compound semiconductor substrate with a prescribed lattice constant for loading the double heterostructure section, a lattice mismatched active layer with a first lattice constant which is 0.5% to 2.0% larger than the lattice constant of the substrate in the double heterostructure section for radiating the laser beam, a lattice mismatched cladding layer with a second lattice constant which is 0.2% to 2.0% smaller than the lattice constant of the substrate for confining the injected carriers in the active layer, and a cladding layer for confining the injected carriers in the active layer by co-operating with the lattice mismatched cladding layer.Type: GrantFiled: June 9, 1992Date of Patent: January 25, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Masaki Okajima, Koichi Nitta, Genichi Hatakoshi, Yukie Nishikawa, Kazuhiko Itaya