Patents by Inventor Yukiharu Takeuchi

Yukiharu Takeuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10006565
    Abstract: A fixation member configured to fix a filler pipe to the vehicle body includes a flexural deformation portion. In a non-surrounded state, this flexural deformation portion is not flexurally deformed but is located on the inner side of the outer circumference of a filler neck body. In a surrounded state, the flexural deformation portion is flexurally deformed to induce a pressing force and provides the pressing force to the filler pipe. This configuration suppresses rattling of the filler pipe over a long time period.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: June 26, 2018
    Assignee: TOYODA GOSEI CO., LTD.
    Inventors: Hiroaki Kito, Yoshinari Hiramatsu, Yukiharu Takeuchi, Sanae Noro, Takeshi Aimiya
  • Publication number: 20170089491
    Abstract: A fixation member configured to fix a filler pipe to the vehicle body includes a flexural deformation portion. In a non-surrounded state, this flexural deformation portion is not flexurally deformed but is located on the inner side of the outer circumference of a filler neck body. In a surrounded state, the flexural deformation portion is flexurally deformed to induce a pressing force and provides the pressing force to the filler pipe. This configuration suppresses rattling of the filler pipe over a long time period.
    Type: Application
    Filed: September 12, 2016
    Publication date: March 30, 2017
    Inventors: Hiroaki KITO, Yoshinari HIRAMATSU, Yukiharu TAKEUCHI, Sanae NORO, Takeshi AIMIYA
  • Patent number: 9490221
    Abstract: A semiconductor device includes a wiring substrate, a lower magnetic shield member, a semiconductor chip, and an upper magnetic shield member. The lower magnetic shield member is provided on the wiring substrate. The semiconductor chip is provided on the lower magnetic shield member. The semiconductor chip includes a magnetic memory element. The upper magnetic shield member is provided on the semiconductor chip. The semiconductor chip is disposed between the upper magnetic shield member and the lower magnetic shield member. The lower magnetic shield member and the upper magnetic shield member include a soft magnetic resin. The lower magnetic shield member and the upper magnetic shield member are in direct contact with each other.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: November 8, 2016
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Tadashi Arai, Yukiharu Takeuchi
  • Publication number: 20160093795
    Abstract: A semiconductor device includes a wiring substrate, a lower magnetic shield member, a semiconductor chip, and an upper magnetic shield member. The lower magnetic shield member is provided on the wiring substrate. The semiconductor chip is provided on the lower magnetic shield member. The semiconductor chip includes a magnetic memory element. The upper magnetic shield member is provided on the semiconductor chip. The semiconductor chip is disposed between the upper magnetic shield member and the lower magnetic shield member. The lower magnetic shield member and the upper magnetic shield member include a soft magnetic resin. The lower magnetic shield member and the upper magnetic shield member are in direct contact with each other.
    Type: Application
    Filed: September 30, 2015
    Publication date: March 31, 2016
    Inventors: Tadashi Arai, Yukiharu Takeuchi
  • Patent number: 8853841
    Abstract: A semiconductor package includes a lead frame including a chip mounting portion and a terminal portion, a semiconductor chip, which is mounted on the chip mounting portion and connected to the terminal portion, a through groove penetrating the terminal portion from one surface on a side of the semiconductor chip to another surface in a thickness direction of the terminal portion, a lid portion covering an end portion of the through groove on the side of the semiconductor chip, and a resin portion sealing the semiconductor chip, wherein the another surface of the terminal portion and a side surface of the terminal portion facing an outside of the semiconductor package are coated by a plating film.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: October 7, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Yukiharu Takeuchi
  • Patent number: 8729680
    Abstract: A semiconductor device includes a structure in which a semiconductor element (chip) is mounted in a cavity formed in a wiring board with an adhesive interposed between the chip and a bottom surface of the cavity, and electrode terminals of the chip are connected via wires to wiring portions formed on the board around the cavity. The chip is mounted in close contact with a side wall of the cavity, the side wall being near a region where a wiring for higher frequency compared with other wirings within the wiring portion is formed. A recessed portion is provided in a region of the bottom surface of the cavity, and a thermal via extending from the bottom surface of the recessed to the outside of the board is provided, the region being near a portion where the chip is in close contact.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: May 20, 2014
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Narue Kobayashi, Tomoharu Fujii, Yukiharu Takeuchi
  • Publication number: 20130277817
    Abstract: A semiconductor package includes a lead frame including a chip mounting portion and a terminal portion, a semiconductor chip, which is mounted on the chip mounting portion and connected to the terminal portion, a through groove penetrating the terminal portion from one surface on a side of the semiconductor chip to another surface in a thickness direction of the terminal portion, a lid portion covering an end portion of the through groove on the side of the semiconductor chip, and a resin portion sealing the semiconductor chip, wherein the another surface of the terminal portion and a side surface of the terminal portion facing an outside of the semiconductor package are coated by a plating film.
    Type: Application
    Filed: April 3, 2013
    Publication date: October 24, 2013
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Yukiharu TAKEUCHI
  • Patent number: 8525355
    Abstract: There is provided a semiconductor device which includes a primary semiconductor chip 11, a secondary semiconductor chip 12 stacked on the primary semiconductor chip 11, primary external connecting terminals 16 which are electrically connected with the primary semiconductor chip 11 via wires 21, secondary external connecting terminals 17 which are electrically connected with the secondary semiconductor chip 12 via wires 22 and primary and secondary low-elasticity resins 13, 15 which seal the primary and secondary semiconductor chips 11, 12 in such a manner as to cover them.
    Type: Grant
    Filed: April 18, 2007
    Date of Patent: September 3, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Hidenori Takayanagi, Yukiharu Takeuchi, Hiroki Toyazaki, Toshio Gomyo
  • Publication number: 20130163206
    Abstract: A semiconductor device includes a structure in which a semiconductor element (chip) is mounted in a cavity formed in a wiring board with an adhesive interposed between the chip and a bottom surface of the cavity, and electrode terminals of the chip are connected via wires to wiring portions formed on the board around the cavity. The chip is mounted in close contact with a side wall of the cavity, the side wall being near a region where a wiring for higher frequency compared with other wirings within the wiring portion is formed. A recessed portion is provided in a region of the bottom surface of the cavity, and a thermal via extending from the bottom surface of the recessed to the outside of the board is provided, the region being near a portion where the chip is in close contact.
    Type: Application
    Filed: November 14, 2012
    Publication date: June 27, 2013
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Narue Kobayashi, Tomoharu Fujii, Yukiharu Takeuchi
  • Patent number: 8402644
    Abstract: A method of manufacturing an electronic parts packaging structure including the steps of preparing a plurality of sheet-like units each of which is constructed by a first insulating layer, a wiring formed on one surface of the first insulating layer, electronic parts connected to the wiring, a second insulating layer formed on an one surface side of the first insulating layer to cover the electronic parts, and a connecting portion for connecting electrically the wiring, and stacking mutually the units to arrange directions of unit adjacent in a thickness direction alternately oppositely, and bonding the units such that electronic parts of respective units are electrically connected mutually via connecting portions.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: March 26, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Toshio Gomyo, Yukiharu Takeuchi, Hidenori Takayanagi, Takaharu Yamano
  • Patent number: 8373997
    Abstract: A semiconductor device includes a structure in which a semiconductor element (chip) is mounted in a cavity formed in a wiring board with an adhesive interposed between the chip and a bottom surface of the cavity, and electrode terminals of the chip are connected via wires to wiring portions formed on the board around the cavity. The chip is mounted in close contact with a side wall of the cavity, the side wall being near a region where a wiring for higher frequency compared with other wirings within the wiring portion is formed. A recessed portion is provided in a region of the bottom surface of the cavity, and a thermal via extending from the bottom surface of the recessed to the outside of the board is provided, the region being near a portion where the chip is in close contact.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: February 12, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Narue Kobayashi, Tomoharu Fujii, Yukiharu Takeuchi
  • Patent number: 8191568
    Abstract: A fuel tank capable of attaching functional parts and tubes in an interior thereof. In a fuel tank for a motor vehicle, which is formed by blow molding for attachment of a built-in part in an interior thereof, and of which an outer wall composed of a synthetic resin has an opening, a functional part adapted to discharge fluid from the interior of the fuel tank or feed fluid therein is attached to the built-in part, a tube adapted to discharge fluid from the interior of the fuel tank or feed fluid therein is connected to the functional part, and a tube connector is attached to an end of the tube. A temporal holding connector is formed integrally with the built-in part, the tube connector is attached to the temporal holding connector, and after blow molding, the tube connector is detached from the temporal holding connector and is attached to a tank cap adapted to close the opening of the fuel tank.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: June 5, 2012
    Assignees: Toyoda Gosei Co., Ltd., FTS Co., Ltd.
    Inventors: Yukiharu Takeuchi, Norihiro Yamada, Hideyuki Tsuzuki, Tomohide Aoki
  • Publication number: 20120133056
    Abstract: There is provided a semiconductor device which includes a primary semiconductor chip 11, a secondary semiconductor chip 12 stacked on the primary semiconductor chip 11, primary external connecting terminals 16 which are electrically connected with the primary semiconductor chip 11 via wires 21, secondary external connecting terminals 17 which are electrically connected with the secondary semiconductor chip 12 via wires 22 and primary and secondary low-elasticity resins 13, 15 which seal the primary and secondary semiconductor chips 11, 12 in such a manner as to cover them.
    Type: Application
    Filed: February 8, 2012
    Publication date: May 31, 2012
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Hidenori Takayanagi, Yukiharu Takeuchi, Hiroki Toyazaki, Toshio Gomyo
  • Patent number: 8053677
    Abstract: An electronic apparatus includes a multilayer wiring structure having insulating layers and wiring layers which are stacked and having a surface on which an electronic component is mounted, a dipole antenna formed on a surface 13A of the multilayer wiring structure, a radiating plate disposed on the surface together with the dipole antenna, and a radiating path formed in the multilayer wiring structure and serving to transfer a heat generated in the electronic component to the radiating plate.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: November 8, 2011
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Tomoharu Fujii, Yukiharu Takeuchi
  • Publication number: 20110156228
    Abstract: A semiconductor device includes a structure in which a semiconductor element (chip) is mounted in a cavity formed in a wiring board with an adhesive interposed between the chip and a bottom surface of the cavity, and electrode terminals of the chip are connected via wires to wiring portions formed on the board around the cavity. The chip is mounted in close contact with a side wall of the cavity, the side wall being near a region where a wiring for higher frequency compared with other wirings within the wiring portion is formed. A recessed portion is provided in a region of the bottom surface of the cavity, and a thermal via extending from the bottom surface of the recessed to the outside of the board is provided, the region being near a portion where the chip is in close contact.
    Type: Application
    Filed: December 20, 2010
    Publication date: June 30, 2011
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Narue Kobayashi, Tomoharu Fujii, Yukiharu Takeuchi
  • Publication number: 20110039370
    Abstract: In an electronic parts packaging structure of the present invention constructed by stacking a plurality of sheet-like units in a thickness direction, each of the units includes a first insulating layer, wirings formed on one surface of the first insulating layer, a semiconductor chip (electronic parts) connected to the wirings, a second insulating layer formed on an one surface side of the first insulating layer to cover the semiconductor chip, and connecting portions (terminals and contact vias) for connecting electrically the wirings and wirings of other unit, wherein arrangement of the first insulating layer, the semiconductor chip, the wirings, and the second insulating layer is symmetrical between units adjacent in a thickness direction.
    Type: Application
    Filed: October 25, 2010
    Publication date: February 17, 2011
    Applicant: Shinko Electric Industries Co., Ltd.
    Inventors: Toshio Gomyo, Yukiharu Takeuchi, Hidenori Takayanagi, Takaharu Yamano
  • Patent number: 7843059
    Abstract: In an electronic parts packaging structure of the present invention constructed by stacking a plurality of sheet-like units in a thickness direction, each of the units includes a first insulating layer, wirings formed on one surface of the first insulating layer, a semiconductor chip (electronic parts) connected to the wirings, a second insulating layer formed on an one surface side of the first insulating layer to cover the semiconductor chip, and connecting portions (terminals and contact vias) for connecting electrically the wirings and wirings of other unit, wherein arrangement of the first insulating layer, the semiconductor chip, the wirings, and the second insulating layer is symmetrical between units adjacent in a thickness direction.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: November 30, 2010
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Toshio Gomyo, Yukiharu Takeuchi, Hidenori Takayanagi, Takaharu Yamano
  • Patent number: 7816177
    Abstract: In a semiconductor device, via holes are formed around a chip buried in a package, one end of a conductor filled in the via hole is covered with a pad portion exposed to the outside, and a wiring layer connected to the other end of the conductor is formed. The portion (pad portion) of the wiring layer which correspond to the conductor is exposed from a protective film, or an external connection terminal is bonded to the top of the pad portion. Electrode terminals of the chip are connected to the wiring layer, and the opposite surface of the chip is exposed to the outside.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: October 19, 2010
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Yukiharu Takeuchi, Hidenori Takayanagi
  • Patent number: 7791206
    Abstract: In a semiconductor device, via holes are formed around a chip buried in a package, and conductor layers are respectively formed to be connected to one end and another end of the conductor filled in the individual via hole. Portions (pad portions) of the conductor layers which correspond to the conductors are exposed from protective films, or external connection terminals are bonded to the pad portions. The chip is mounted with flip-chip technology so that at least some of electrode terminals thereof are electrically connected to the conductor layers.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: September 7, 2010
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Yukiharu Takeuchi, Hidenori Takayanagi
  • Patent number: 7788061
    Abstract: A substrate and mask aligning apparatus includes a controlling portion 70 for calculating moving data that are applied to eliminate a difference between a present superposed state of the through holes 52 of the mask 50, which comes into contact with the substrate 20 that is loaded on the stage 30, on the pads 22 of the substrate 20 and a scheduled superposed state on the basis of image data from the shooting section 40, 42 and then executing repeatedly an operation to move the stage 30 on the basis of the calculated moving data of the stage.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: August 31, 2010
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Yukiharu Takeuchi, Hideaki Sakaguchi