Abstract: In a semiconductor device, via holes are formed around a chip buried in a package, one end of a conductor filled in the via hole is covered with a pad portion exposed to the outside, and a wiring layer connected to the other end of the conductor is formed. The portion (pad portion) of the wiring layer which correspond to the conductor is exposed from a protective film, or an external connection terminal is bonded to the top of the pad portion. Electrode terminals of the chip are connected to the wiring layer, and the opposite surface of the chip is exposed to the outside.

Abstract: In a semiconductor device, via holes are formed around a chip buried in a package, one end of a conductor filled in the via hole is covered with a pad portion exposed to the outside, and a wiring layer connected to the other end of the conductor is formed. The portion (pad portion) of the wiring layer which correspond to the conductor is exposed from a protective film, or an external connection terminal is bonded to the top of the pad portion. Electrode terminals of the chip are connected to the wiring layer, and the opposite surface of the chip is exposed to the outside.

Abstract: A fuel tank capable of attaching functional parts and tubes in an interior thereof. In a fuel tank for a motor vehicle, which is formed by blow molding for attachment of a built-in part in an interior thereof, and of which an outer wall composed of a synthetic resin has an opening, a functional part adapted to discharge fluid from the interior of the fuel tank or feed fluid therein is attached to the built-in part, a tube adapted to discharge fluid from the interior of the fuel tank or feed fluid therein is connected to the functional part, and a tube connector is attached to an end of the tube. A temporal holding connector is formed integrally with the built-in part, the tube connector is attached to the temporal holding connector, and after blow molding, the tube connector is detached from the temporal holding connector and is attached to a tank cap adapted to close the opening of the fuel tank.

Abstract: An electronic apparatus includes a multilayer wiring structure having insulating layers and wiring layers which are stacked and having a surface on which an electronic component is mounted, a dipole antenna formed on a surface 13A of the multilayer wiring structure, a radiating plate disposed on the surface together with the dipole antenna, and a radiating path formed in the multilayer wiring structure and serving to transfer a heat generated in the electronic component to the radiating plate.

Abstract: A substrate and mask aligning apparatus includes a controlling portion 70 for calculating moving data that are applied to eliminate a difference between a present superposed state of the through holes 52 of the mask 50, which comes into contact with the substrate 20 that is loaded on the stage 30, on the pads 22 of the substrate 20 and a scheduled superposed state on the basis of image data from the shooting section 40, 42 and then executing repeatedly an operation to move the stage 30 on the basis of the calculated moving data of the stage.

Abstract: There is provided a semiconductor device which includes a primary semiconductor chip 11, a secondary semiconductor chip 12 stacked on the primary semiconductor chip 11, primary external connecting terminals 16 which are electrically connected with the primary semiconductor chip 11 via wires 21, secondary external connecting terminals 17 which are electrically connected with the secondary semiconductor chip 12 via wires 22 and primary and secondary low-elasticity resins 13, 15 which seal the primary and secondary semiconductor chips 11, 12 in such a manner as to cover them.

Abstract: In a capacitor-mounted wiring board, a plurality of wiring layers each patterned in a required shape are stacked with insulating layers interposed therebetween and are connected to each other via conductors formed to pierce the insulating layers in the direction of thickness. A decoupling capacitor is electrically connected to a wiring layer used as a power supply line or a ground line in the vicinity of the wiring layer, and mounted such that, when a current is passed through the capacitor, the direction of the current is reversed to that of the current flowing through the relevant wiring layer.

Abstract: In an electronic parts packaging structure of the present invention constructed by stacking a plurality of sheet-like units in a thickness direction, each of the units includes a first insulating layer, wirings formed on one surface of the first insulating layer, a semiconductor chip (electronic parts) connected to the wirings, a second insulating layer formed on an one surface side of the first insulating layer to cover the semiconductor chip, and connecting portions (terminals and contact vias) for connecting electrically the wirings and wirings of other unit, wherein arrangement of the first insulating layer, the semiconductor chip, the wirings, and the second insulating layer is symmetrical between units adjacent in a thickness direction.

Abstract: In a capacitor-mounted wiring board, a plurality of wiring layers each patterned in a required shape are stacked with insulating layers interposed therebetween and are connected to each other via conductors formed to pierce the insulating layers in the direction of thickness. A decoupling capacitor is electrically connected to a wiring layer used as a power supply line or a ground line in the vicinity of the wiring layer, and mounted such that, when a current is passed through the capacitor, the direction of the current is reversed to that of the current flowing through the relevant wiring layer.

Abstract: In a semiconductor device, via holes are formed around a chip buried in a package, and conductor layers are respectively formed to be connected to one end and another end of the conductor filled in the individual via hole. Portions (pad portions) of the conductor layers which correspond to the conductors are exposed from protective films, or external connection terminals are bonded to the pad portions. The chip is mounted with flip-chip technology so that at least some of electrode terminals thereof are electrically connected to the conductor layers.

Abstract: In a semiconductor device, via holes are formed around a chip buried in a package, one end of a conductor filled in the via hole is covered with a pad portion exposed to the outside, and a wiring layer connected to the other end of the conductor is formed. The portion (pad portion) of the wiring layer which correspond to the conductor is exposed from a protective film, or an external connection terminal is bonded to the top of the pad portion. Electrode terminals of the chip are connected to the wiring layer, and the opposite surface of the chip is exposed to the outside.

Abstract: A lead frame for semiconductor device comprising inner leads, outer leads, and dam bars, the inner leads being divided into two groups which are located in opposed areas of the lead frame divided by the center line of the array of the electrode pads of a semiconductor chip to be mounted on the lead frame, and the inner lead having a first end and a second end, the first ends of the respective inner leads being arranged into arrays along an array of electrode pads of the semiconductor chip, so that the array of the first ends has a pitch corresponding to a pitch in the array of the electrode pads, the second ends of the respective inner leads being arranged into arrays at opposed sides of the lead frame, to have a pitch larger than the pitch in the array of the first ends, wherein at least some of the inner leads are arranged to have lengths between the first and the second ends which are substantially equivalent to each other. A semiconductor device using the lead frame is also disclosed.

Abstract: A semiconductor device is provided which improves reliability by preventing connection defects with extensions and interface peeling occurring between a substrate and a sealing resin, and which can reduce the production cost by simplifying a fabrication process. In this semiconductor device, each lead 16 for electrically connecting an electrode terminal 12 of a semiconductor chip to an external connection terminal 14 comprises an extension 17 extending parallel to an electrode terminal formation surface of the semiconductor chip 10 with a predetermined distance from the electrode terminal formation surface, an external connection terminal post 22 provided to one of the end portions of the extension 17, and an electrode terminal post 24 connected to the electrode terminal 12 of the semiconductor chip 10. The electrode terminal post 22 and the extension 17 are sealed by a sealing resin 18, and the distal end portion of the external connection terminal post 24 is exposed from the sealing resin 18.

Abstract: A multi-layer circuit board having a decreased number of circuit boards for mounting an electronic part that has connection electrodes arranged in the form of an area array, featuring a high yield and improved reliability.

Abstract: A semiconductor package capable of quickly and satisfactorily dissipating to the outside the heat generated from a semiconductor chip mounted in it and in turn capable of contributing to an improvement of the operational reliability of the semiconductor chip, provided with an interconnection substrate, a heat dissipation plate bonded to one surface of the interconnection substrate, a cavity formed in another surface of the interconnection substrate for with mounting a semiconductor chip, a plurality of external connection terminals arranged in a grid on the other surface of the interconnection substrate around the cavity, and through holes formed with conductor layers on their inside walls formed at a periphery of the interconnection substrate and penetrating through the interconnection substrate so as to reach the heat dissipation plate, and a semiconductor device using the same.

Abstract: A semiconductor device comprising a semiconductor chip having an electrode terminal carrying surface and electrode terminals formed on, and carried by, the electrode terminal carrying surface; leads extending substantially parallel to the electrode terminal carrying surface and each having at least one curved portion; a first bump and a second bump which are formed on one and the other ends, respectively, of each of the leads and protrude from the ends in opposite directions toward and away from, respectively, the electrode terminal carrying surface; and the electrode terminals of the semiconductor chip each being bonded to a top of the first bump of the lead to support the leads at a distance from the electrode terminal carrying surface of the semiconductor chip. A process of producing the semiconductor device a dissolvable metal sheet suitably used in the process and a process of producing the metal sheet are also provided.

Abstract: A multi-layer circuit board formed by laminating a plurality of circuit boards each having lands arranged in many number in the form of a lattice or in a staggering manner on the side of the mounting surface and having circuit patterns with the ends on one side thereof being connected to said lands and with the ends on the other side thereof being drawn toward the outside from a region where said lands are arranged; wherein the lands for drawing the circuit patterns in a number not less than a+1 are arranged on the oblique lines of an isosceles triangle having a base formed by consecutive lands of a number of n and having oblique lines in the diagonal directions, the value n satisfying m≧k+1 of the two values of: m={(land pitch)×(n−1)−(land diameter)−(space between patterns)}÷(pattern width+space between patterns), k=a(n−1)+(n−2), wherein “a” is the number of the circuit patterns that can be arranged betwe

Abstract: A wiring substrate is provided in which a common core member is used and the cost can be reduced. Diameters of the penetrating filled vias (18) are the same and not more than 300 .mu.m, and the penetrating filled vias (18) are formed on a core substrate (20) into a matrix-shape at regular intervals of not more than 2 mm. On the surface of the core substrate (20), a plane wiring pattern (17) is formed through an insulating layer (16). Each pad portion on the wiring pattern (17) is electrically connected with each corresponding via of the filled vias (18) by one to one through a connecting via (28) which penetrates the insulating layer (16), and some of the filled vias (18) are not connected with the wiring pattern (17).

Abstract: A sintered body, for manufacturing a ceramic substrate, on which a via can be formed with high positional accuracy and the substrate is not warped and further the productivity is high. The sintered body includes a pillar-shaped ceramic body and metallic wiring rods provided in the ceramic body in parallel with the axis. The metallic wiring rods are made of metal, the melting point of which is lower than the sintering temperature of the sintered ceramic body.

Abstract: A hose 10 of the invention includes an outer hose member 12 composed of a rubber and an inner hose member 14 composed of a resin. A pair of projection ring elements 26 formed on opposite ends of the inner hose member 14 are received in a pair of inner circumferential grooves 24 formed in thick-walled tube elements 18 of the outer hose member 12. The projection ring elements extend the inner circumferential grooves 24 with such dilatation and deformation of the concavity of the inner circumferential grooves 24 enabling the thick-walled tube elements 18 to generate forces acting along the concavity of the inner circumferential grooves 24. Such forces are applied as pressing forces against the projection ring elements 26. The thick wall of the thick-walled tube elements 18 enables the pressing forces to be maintained while the projection ring elements 26 are retained in the inner circumferential grooves 24.