Abstract: A three-dimensional memory device includes an alternating stacks of insulating layers and electrically conductive layers. Memory opening fill structures located in memory openings include a memory film and plural vertical semiconductor channels.

Abstract: A three-dimensional memory device includes an alternating stacks of insulating layers and electrically conductive layers. Memory opening fill structures located in memory openings include a memory film and plural vertical semiconductor channels.

Abstract: A semiconductor die can include an alternating stack of insulating layers and electrically conductive layers located on a substrate, memory stack structures extending through the alternating stack, drain regions located at a first end of a respective one of the vertical semiconductor channels of a memory stack structure, and bit lines extending over the drain regions and electrically connected to a respective subset of the drain regions. At least of a subset of the bit lines includes bump-containing bit lines. Each of the bump-containing bit lines includes a line portion and a bump portion that protrudes upward from a top surface of the line portion by a bump height. Bit line contact via structures overlie the bit lines and contact a bump portion of a respective one of the bump-containing bit lines.

Abstract: A semiconductor die can include an alternating stack of insulating layers and electrically conductive layers located on a substrate, memory stack structures extending through the alternating stack, drain regions located at a first end of a respective one of the vertical semiconductor channels of a memory stack structure, and bit lines extending over the drain regions and electrically connected to a respective subset of the drain regions. At least of a subset of the bit lines includes bump-containing bit lines. Each of the bump-containing bit lines includes a line portion and a bump portion that protrudes upward from a top surface of the line portion by a bump height. Bit line contact via structures overlie the bit lines and contact a bump portion of a respective one of the bump-containing bit lines.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings extending through the alternating stack, memory opening fill structures located within a respective one of the memory openings, and a gate dielectric located between the memory opening fill structures and the electrically conductive layers. Each of the memory opening fill structures includes a vertical semiconductor channel, a conductive core electrode, and a memory film located between the vertical semiconductor channel and the conductive core electrode. The memory film contains a layer stack including a first tunneling dielectric contacting the vertical semiconductor channel, a second tunneling dielectric contacting the conductive core electrode, and a charge storage layer located between the first tunneling dielectric and the second tunneling dielectric.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings extending through the alternating stack, memory opening fill structures located within a respective one of the memory openings, and a gate dielectric located between the memory opening fill structures and the electrically conductive layers. Each of the memory opening fill structures includes a vertical semiconductor channel, a conductive core electrode, and a memory film located between the vertical semiconductor channel and the conductive core electrode. The memory film contains a layer stack including a first tunneling dielectric contacting the vertical semiconductor channel, a second tunneling dielectric contacting the conductive core electrode, and a charge storage layer located between the first tunneling dielectric and the second tunneling dielectric.

Abstract: A non-volatile memory system is provided that includes a plurality of NAND strings of non-volatile storage elements, each non-volatile storage element including a control gate, a tunneling layer, a floating gate, and a blocking layer including a ferroelectric material. The tunneling layer is disposed between the control gate and the floating gate, and the floating gate is disposed between the tunneling layer and the blocking layer.

Abstract: A non-volatile memory system is provided that includes a plurality of NAND strings of non-volatile storage elements, each non-volatile storage element including a control gate, a tunneling layer, a floating gate, and a blocking layer including a ferroelectric material. The tunneling layer is disposed between the control gate and the floating gate, and the floating gate is disposed between the tunneling layer and the blocking layer.

Abstract: A non-volatile storage element is provided that includes a control gate, a blocking layer including a ferroelectric material, a charge storage region, and a tunneling layer. The blocking layer is disposed between the control gate and the charge storage region, and the charge storage region is disposed between the tunneling layer and the blocking layer.

Abstract: A memory cell is provided that includes a control gate, a tunneling layer, a charge storage region, a blocking layer including a ferroelectric material, a semiconductor channel, and a source region and a drain region each disposed adjacent the semiconductor channel. The tunneling layer is disposed between the control gate and the charge storage region, the charge storage region is disposed between the tunneling layer and the blocking layer, and the blocking layer is disposed above the semiconductor channel.

Abstract: A non-volatile storage element including a control gate, a tunneling layer, a charge storage region, and a blocking layer including a ferroelectric material. The tunneling layer is disposed between the control gate and the charge storage region, and the charge storage region is disposed between the tunneling layer and the blocking layer.

Abstract: A non-volatile storage element including a control gate, a tunneling layer, a charge storage region, and a blocking layer including a ferroelectric material. The tunneling layer is disposed between the control gate and the charge storage region, and the charge storage region is disposed between the tunneling layer and the blocking layer.

Abstract: A non-volatile storage element is provided that includes a control gate, a blocking layer including a ferroelectric material, a charge storage region, and a tunneling layer. The blocking layer is disposed between the control gate and the charge storage region, and the charge storage region is disposed between the tunneling layer and the blocking layer.

Abstract: A memory cell is provided that includes a control gate, a tunneling layer, a charge storage region, a blocking layer including a ferroelectric material, a semiconductor channel, and a source region and a drain region each disposed adjacent the semiconductor channel.

Abstract: A middle electrode can be inserted at each intersection between a non-volatile memory element layer located on an electrically conductive word line and a non-linear element located on an electrically conductive bit line in a three-dimensional memory device. An oxygen-scavenging material portion can be provided between each electrically conductive word line and an adjoining insulator layer to scavenge oxygen from contacting portions of the non-volatile memory element layer, thereby forming an oxygen-scavenged non-volatile memory element portion that facilitates programming. The middle electrode and the oxygen-scavenged non-linear memory element portion can alter the programming characteristics of the non-volatile memory cells to provide easier and more reliable programming.

Abstract: A middle electrode can be inserted at each intersection between a non-volatile memory element layer located on an electrically conductive word line and a non-linear element located on an electrically conductive bit line in a three-dimensional memory device. An oxygen-scavenging material portion can be provided between each electrically conductive word line and an adjoining insulator layer to scavenge oxygen from contacting portions of the non-volatile memory element layer, thereby forming an oxygen-scavenged non-volatile memory element portion that facilitates programming. The middle electrode and the oxygen-scavenged non-linear memory element portion can alter the programming characteristics of the non-volatile memory cells to provide easier and more reliable programming.

Abstract: A monolithic, three-dimensional memory device includes a substrate and a plurality of electrically conductive word lines over a major surface of the substrate. An electrically conductive bit line extends in a direction substantially perpendicular to the major surface of the substrate and adjacent to each of the plurality of word lines, and a non-volatile memory element material is located between the bit line and each of the plurality of word lines. A plurality of middle electrodes comprising an electrically conductive material are located between the bit line and each of the plurality of word lines, wherein the plurality of middle electrodes are discrete electrodes which are isolated from one another in at least the second direction.

Abstract: A monolithic, three-dimensional memory device includes a substrate and a plurality of electrically conductive word lines over a major surface of the substrate. An electrically conductive bit line extends in a direction substantially perpendicular to the major surface of the substrate and adjacent to each of the plurality of word lines, and a non-volatile memory element material is located between the bit line and each of the plurality of word lines. A plurality of middle electrodes comprising an electrically conductive material are located between the bit line and each of the plurality of word lines, wherein the plurality of middle electrodes are discrete electrodes which are isolated from one another in at least the second direction.

Abstract: A semiconductor device includes at least first and second electrodes, and a layer including a transition metal oxide layer sandwiched between the first and second electrodes. The transition metal oxide layer includes first and second transition metal oxide layers formed of different first and second transition metals, respectively. The first transition metal oxide layer is provided on the first electrode side, the second transition metal oxide layer is provided on the second electrode side, the first transition metal oxide layer and the second transition metal oxide layer are in contact with each other, the first transition metal oxide layer has an oxygen concentration gradient from the interface between the first transition metal oxide layer and the second transition metal oxide layer toward the first electrode side, and the oxygen concentration at the interface is greater than the oxygen concentration on the first electrode side.

Abstract: Provided is a resistance change type nonvolatile semiconductor storage device including a diode capable of passing therethrough a sufficient current to a resistance changing operation even when the memory cell is miniaturized. A nonvolatile semiconductor storage device has first wires extending in X direction, second wires extending in Y direction, and memory cells disposed at intersection points of the first wires and the second wires. The memory cell includes a diode disposed over the first wire, and coupled to the first wire at one end, and a resistance change part disposed over the diode, and series-coupled to the diode at one end, and coupled to the second wire at the other end, and storing information through changes in resistance value. The diode includes a first conductivity type first semiconductor layer, and a second conductivity type second semiconductor layer extending into the inside of the first semiconductor layer.