Patents by Inventor Yukihiro Satou
Yukihiro Satou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7928589Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.Type: GrantFiled: May 12, 2009Date of Patent: April 19, 2011Assignee: Renesas Electronics CorporationInventors: Yukihiro Satou, Tomoaki Uno, Nobuyoshi Matsuura, Masaki Shiraishi
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Patent number: 7911054Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.Type: GrantFiled: March 25, 2009Date of Patent: March 22, 2011Assignees: Renesas Electronics Corporation, Hitachi Hokkai Semiconductor Ltd.Inventors: Hajime Hasebe, Tadatoshi Danno, Yukihiro Satou
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Publication number: 20100321969Abstract: A semiconductor device capable of reducing an inductance is provided. In the semiconductor device in which a rectification MOSFET, a commutation MOSFET, and a driving IC that drives these MOSFETs are mounted on one package, the rectification MOSFET, a metal plate, and the commutation MOSFET are laminated. A current of a main circuit flows from a back surface of the package to a front surface thereof. The metal plate is connected to an output terminal via a wiring in the package. Wire bondings are used for wirings for connecting the driving IC, the rectification MOSFET, and the commutation MOSFET, all terminals being placed on the same plane. For this reason, the inductance becomes small and also a power source loss and a spike voltage are reduced.Type: ApplicationFiled: August 6, 2010Publication date: December 23, 2010Inventors: Takayuki Hashimoto, Nobuyoshi Matsuura, Masaki Shiraishi, Yukihiro Satou, Tetsuya Kawashima
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Publication number: 20100276798Abstract: A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad.Type: ApplicationFiled: July 13, 2010Publication date: November 4, 2010Inventors: Yukihiro Satou, Toshiyuki Hata
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Patent number: 7800215Abstract: A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad.Type: GrantFiled: April 28, 2009Date of Patent: September 21, 2010Assignee: Renesas Electronics CorporationInventors: Yukihiro Satou, Toshiyuki Hata
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Patent number: 7782025Abstract: A semiconductor device capable of reducing an inductance is provided. In the semiconductor device in which a rectification MOSFET, a commutation MOSFET, and a driving IC that drives these MOSFETs are mounted on one package, the rectification MOSFET, a metal plate, and the commutation MOSFET are laminated. A current of a main circuit flows from a back surface of the package to a front surface thereof. The metal plate is connected to an output terminal via a wiring in the package. Wire bondings are used for wirings for connecting the driving IC, the rectification MOSFET, and the commutation MOSFET, all terminals being placed on the same plane. For this reason, the inductance becomes small and also a power source loss and a spike voltage are reduced.Type: GrantFiled: January 6, 2009Date of Patent: August 24, 2010Assignee: Renesas Electronics Corp.Inventors: Takayuki Hashimoto, Nobuyoshi Matsuura, Masaki Shiraishi, Yukihiro Satou, Tetsuya Kawashima
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Publication number: 20100193934Abstract: A novel semiconductor device high in both heat dissipating property and connection reliability in mounting is to be provided. The semiconductor device comprises a semiconductor chip, a resin sealing member for sealing the semiconductor chip, a first conductive member connected to a first electrode formed on a first main surface of the semiconductor chip, and a second conductive member connected to a second electrode formed on a second main surface opposite to the first main surface of the semiconductor chip, the first conductive member being exposed from a first main surface of the resin sealing member, and the second conductive member being exposed from a second main surface opposite to the first main surface of the resin sealing member and also from side faces of the resin sealing member.Type: ApplicationFiled: April 13, 2010Publication date: August 5, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Yukihiro Satou, Takeshi Otani, Hiroyuki Takahashi, Toshiyuki Hata, Ichio Shimizu
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Publication number: 20100141229Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS·FET for a high side switch and a power MOS·FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.Type: ApplicationFiled: February 18, 2010Publication date: June 10, 2010Inventors: Yukihiro SATOU, Tomoaki Uno, Nobuyoshi Matsuura, Masaki Shiraishi
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Patent number: 7728416Abstract: A novel semiconductor device high in both heat dissipating property and connection reliability in mounting is to be provided. The semiconductor device comprises a semiconductor chip, a resin sealing member for sealing the semiconductor chip, a first conductive member connected to a first electrode formed on a first main surface of the semiconductor chip, and a second conductive member connected to a second electrode formed on a second main surface opposite to the first main surface of the semiconductor chip, the first conductive member being exposed from a first main surface of the resin sealing member, and the second conductive member being exposed from a second main surface opposite to the first main surface of the resin sealing member and also from side faces of the resin sealing member.Type: GrantFiled: June 5, 2008Date of Patent: June 1, 2010Assignee: Renesas Technology Corp.Inventors: Yukihiro Satou, Takeshi Otani, Hiroyuki Takahashi, Toshiyuki Hata, Ichio Shimizu
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Publication number: 20090218683Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.Type: ApplicationFiled: May 12, 2009Publication date: September 3, 2009Inventors: Yukihiro Satou, Tomoaki Uno, Nobuyoshi Matsuura, Masaki Shiraishi
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Publication number: 20090189260Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.Type: ApplicationFiled: March 25, 2009Publication date: July 30, 2009Applicants: RENESAS TECHNOLOGY CORP., HITACHI HOKKAI SEMICONDUCTOR, LTD.Inventors: Hajime HASEBE, Tadatoshi DANNO, Yukihiro SATOU
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Patent number: 7554181Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.Type: GrantFiled: February 9, 2005Date of Patent: June 30, 2009Assignee: Renesas Technology Corp.Inventors: Yukihiro Satou, Tomoaki Uno, Nobuyoshi Matsuura, Masaki Shiraishi
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Patent number: 7554209Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.Type: GrantFiled: March 1, 2007Date of Patent: June 30, 2009Assignee: Renesas Technology Corp.Inventors: Yukihiro Satou, Tomoaki Uno, Nobuyoshi Matsuura, Masaki Shiraishi
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Publication number: 20090154209Abstract: A semiconductor device capable of reducing an inductance is provided. In the semiconductor device in which a rectification MOSFET, a commutation MOSFET, and a driving IC that drives these MOSFETs are mounted on one package, the rectification MOSFET, a metal plate, and the commutation MOSFET are laminated. A current of a main circuit flows from a back surface of the package to a front surface thereof. The metal plate is connected to an output terminal via a wiring in the package. Wire bondings are used for wirings for connecting the driving IC, the rectification MOSFET, and the commutation MOSFET, all terminals being placed on the same plane. For this reason, the inductance becomes small and also a power source loss and a spike voltage are reduced.Type: ApplicationFiled: January 6, 2009Publication date: June 18, 2009Inventors: Takayuki Hashimoto, Nobuyoshi Matsuura, Masaki Shiraishi, Yukihiro Satou, Tetsuya Kawashima
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Patent number: 7541672Abstract: A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad.Type: GrantFiled: June 12, 2006Date of Patent: June 2, 2009Assignee: Renesas Technology Corp.Inventors: Yukihiro Satou, Toshiyuki Hata
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Patent number: 7518156Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.Type: GrantFiled: September 22, 2003Date of Patent: April 14, 2009Assignees: Renesas Technology Corp., Hitachi Hokkai Semiconductor Ltd.Inventors: Hajime Hasebe, Tadatoshi Danno, Yukihiro Satou
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Publication number: 20090039394Abstract: The present invention enhances voltage conversion efficiency of a semiconductor device. In a non-isolated DC-DC converter that includes a high-side switch power MOSFET and a low-side switch power MOSFET, which are series-connected, the high-side switch power MOSFET and driver circuits for driving the high-side and low-side switch power MOSFETs are formed within one semiconductor chip, whereas the low-side switch power MOSFET is formed in another semiconductor chip. The two semiconductor chips are sealed in a single package.Type: ApplicationFiled: October 8, 2008Publication date: February 12, 2009Inventors: Tomoaki UNO, Masaki Shiraishi, Nobuyoshi Matsuura, Yukihiro Satou
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Patent number: 7480163Abstract: A semiconductor device capable of reducing an inductance is provided. In the semiconductor device in which a rectification MOSFET, a commutation MOSFET, and a driving IC that drives these MOSFETs are mounted on one package, the rectification MOSFET, a metal plate, and the commutation MOSFET are laminated. A current of a main circuit flows from a back surface of the package to a front surface thereof. The metal plate is connected to an output terminal via a wiring in the package. Wire bondings are used for wirings for connecting the driving IC, the rectification MOSFET, and the commutation MOSFET, all terminals being placed on the same plane. For this reason, the inductance becomes small and also a power source loss and a spike voltage are reduced.Type: GrantFiled: October 24, 2006Date of Patent: January 20, 2009Assignee: Renesas Technology Corp.Inventors: Takayuki Hashimoto, Nobuyoshi Matsuura, Masaki Shiraishi, Yukihiro Satou, Tetsuya Kawashima
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Publication number: 20090001559Abstract: A novel semiconductor device high in both heat dissipating property and connection reliability in mounting is to be provided. The semiconductor device comprises a semiconductor chip, a resin sealing member for sealing the semiconductor chip, a first conductive member connected to a first electrode formed on a first main surface of the semiconductor chip, and a second conductive member connected to a second electrode formed on a second main surface opposite to the first main surface of the semiconductor chip, the first conductive member being exposed from a first main surface of the resin sealing member, and the second conductive member being exposed from a second main surface opposite to the first main surface of the resin sealing member and also from side faces of the resin sealing member.Type: ApplicationFiled: June 5, 2008Publication date: January 1, 2009Inventors: Yukihiro Satou, Takeshi Otani, Hiroyuki Takahashi, Toshiyuki Hata, Ichio Shimizu
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Patent number: 7274103Abstract: In a semiconductor module connecting a semiconductor element and a passive element to a printed board, each of connection portions between the semiconductor element and the printed board and between the passive element and the printed board includes a metal with a melting point of 260° C. or higher and an intermetallic compound with a melting point of 260° C. or higher. Specifically, by connecting them using Pb-free solder with a melting point of 260° C. or lower, the printed board capable of lowering in cost, lightening, and reducing back height can be applied to a module board.Type: GrantFiled: November 14, 2005Date of Patent: September 25, 2007Assignee: Renesas Technology Corp.Inventors: Osamu Ikeda, Masahide Okamoto, Yukihiro Satou