Patents by Inventor Yukihiro Ueno

Yukihiro Ueno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220270714
    Abstract: To provide a molecular structure generation method and a non-transitory computer-readable medium storing a program capable of generating various molecular structures while satisfying desired property values so as not to be localized around a specific molecular structure. A molecular structure generation method according to the present invention includes: a selection step of classifying a plurality of initial molecules prepared in advance into clusters based on a feature amount and selecting a starting molecule having a maximum confidence limit value from each of the classified clusters. The method further includes an evolutionary development step of evolving each of the starting molecules. Further the selection step and the evolutionary development step are repeatedly executed for all molecules including the initial molecules and the evolved starting molecules to generate a new molecular structure.
    Type: Application
    Filed: February 11, 2022
    Publication date: August 25, 2022
    Inventors: Takuya Okamoto, Yukihiro ABE, Seiji UENO
  • Publication number: 20090289030
    Abstract: A method of fabricating a printed wiring board that is capable of forming a minute via hole with high accuracy is provided. This method of fabricating a printed wiring board 1 comprises: a step of forming an insulation resin layer on at least one surface side of a core wiring board; a step of forming a first resist layer on a predetermined region of a surface of the insulation resin layer; a step of forming a first metal layer with a plating method on a region of the surface of the insulation resin layer except the region where the first resist layer is formed; and a step of forming a via hole by laser machining using the first metal layer as a mask.
    Type: Application
    Filed: March 3, 2009
    Publication date: November 26, 2009
    Inventor: Yukihiro UENO
  • Publication number: 20090114428
    Abstract: A printed wiring board which is sufficiently prevented from being damaged at the time of heating is provided. This printed wiring board comprises a flexible board having flexibility, a lamination portion which is formed on at least one surface of the flexible board and includes an insulation layer and a conductive layer laminated, and a barrier layer which is disposed between the flexible board and the lamination portion, or between the insulation layer and the conductive layer of the lamination portion and has water-vapor permeability lower than that of the insulation layer of the lamination portion.
    Type: Application
    Filed: August 8, 2008
    Publication date: May 7, 2009
    Inventor: Yukihiro UENO
  • Patent number: 7525188
    Abstract: In a multilayer circuit board of the present invention, a plurality of circuit substrates configured by forming a circuit pattern on an insulating base material are stacked via an insulating layer, a through-hole and a via hole are formed in the layering direction, and laser processability and laser processing speed for a processing laser beam used in formation of the through-hole and the via hole are about the same for the insulating substrate material and the insulating layer.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: April 28, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yukihiro Ueno, Keijiroh Edo
  • Publication number: 20090084583
    Abstract: Provided is a multilayer printed wiring board having a terminal portion of high quality. This multilayer printed wiring board has a flexible portion having flexibility, the flexible portion that can be bent when used, a rigid portion formed continuously with the flexible portion, the rigid portion having greater rigidity than the flexible portion, and a terminal portion formed continuously with the flexible portion at an end portion of the flexible portion. The rigid portion includes a rigid layer having insulation properties. The terminal portion includes an insulating layer formed of the same material as that for the rigid layer, the insulating layer having a conductive layer formed on the surface thereof, the conductive layer having a predetermined terminal pattern and serving as a connecting terminal.
    Type: Application
    Filed: May 16, 2008
    Publication date: April 2, 2009
    Inventor: Yukihiro UENO
  • Patent number: 7455533
    Abstract: An insulating resin layer 50 is formed on a surface of a conductor portion 2 by performing a plating pretreatment to the conductor portion 2 that has been formed on a surface of a wiring board substrate 1, and forming numerous dendrites 3 on the surface of the conductor portion 2 using an electroplating or chemical plating method. The insulating resin layer 50 is then formed by stacking an insulating resin plate 50 that has a semi-cured adhesive layer 40 formed thereon in advance on the conductor portion 2 and the dendrites 3, and then applying pressure and raising temperature for laminate bonding.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: November 25, 2008
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yukihiro Ueno
  • Publication number: 20080286696
    Abstract: In one embodiment, the invention has a step of forming an inner layer circuit pattern portion and a lead pattern portion, a step of forming a dummy pattern that indicates the range of the lead pattern portion on the outer layer base material, a step of forming an interlayer adhesive layer on a surface of the outer layer base material where the dummy pattern has been formed, a step of applying, corresponding to the dummy pattern, a resin film to the interlayer adhesive layer, a step of layering the outer layer base material on the inner layer base material via the interlayer adhesive layer with the position of the resin film matched to the position of the lead pattern portion, a step of forming the outer layer circuit pattern portion corresponding to the inner layer circuit pattern portion, and a step of removing the interlayer adhesive layer and the outer layer base material layered on the resin film.
    Type: Application
    Filed: November 29, 2007
    Publication date: November 20, 2008
    Inventors: Yukihiro Ueno, Masatoshi Mori
  • Publication number: 20080202676
    Abstract: In one embodiment, an inner layer pattern formation step of patterning a conductor layer of an inner layer base material to form an inner layer circuit pattern of an inner layer circuit pattern portion and a lead pattern of a lead pattern portion, a resin film affixing step of affixing a resin film to the lead pattern portion, an outer layer base material layering step of layering/fastening to the inner layer base material an outer layer adhesive layer disposed corresponding to the inner layer circuit pattern portion and an outer layer conductor layer disposed corresponding to the inner layer base material, an outer layer pattern formation step of patterning the outer layer conductor layer to form an outer layer circuit pattern portion corresponding to the inner layer circuit pattern portion, and a resin film peeling step of peeling away the resin film from the lead pattern portion, are provided.
    Type: Application
    Filed: February 27, 2008
    Publication date: August 28, 2008
    Inventors: Yukihiro UENO, Hiroaki OKADA
  • Publication number: 20080171139
    Abstract: In one embodiment, an inner layer circuit pattern portion and a lead pattern portion are formed, an outer layer base material is prepared, an interlayer adhesive layer to which has been affixed in advance an inner layer separation film is prepared, the interlayer adhesive layer is layered on the outer layer base material, a molded inner layer separation film is formed by molding the inner layer separation film, the molded inner layer separation film is positioned on the lead pattern portion and the outer layer base material is layered on the inner layer base material with interposition of the interlayer adhesive layer, a conductor layer of the outer layer base material is patterned to form an outer layer circuit pattern portion, and the molded inner layer separation film is separated from the inner layer base material to remove the interlayer adhesive layer and the outer layer base material.
    Type: Application
    Filed: January 10, 2008
    Publication date: July 17, 2008
    Inventors: Yukihiro UENO, Yuhji TAKAMOTO
  • Publication number: 20080118681
    Abstract: According to an embodiment of the present invention, a printed wiring board manufacturing apparatus being provided with a drum unit having a processing cylinder that holds the printed wiring board material and comprises a cylinder outer circumference and a processing unit that performs processing on the printed wiring board material held by the processing cylinder.
    Type: Application
    Filed: October 1, 2007
    Publication date: May 22, 2008
    Inventor: Yukihiro UENO
  • Patent number: 7240431
    Abstract: A plating resist film 2 is formed on a wiring board substrate 1 as a core material of a multilayer printed wiring board, then a through-hole 3 is formed, and through-hole conductor 4 is formed along the wall surface of the through-hole 3 and the through-hole surface of the plating resist film 2, so that protrusion portion 4a is formed in the through-hole conductor 4. The plating resist film 2 is then stripped off and a panel plating layer 5 is formed on the surface of the wiring board substrate 1 and the through-hole conductor 4 so that the through-hole 4 and the panel plating layer 5 are connected with the protrusion 4a coated, and thus the connection area can be increased.
    Type: Grant
    Filed: October 26, 2005
    Date of Patent: July 10, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yukihiro Ueno
  • Publication number: 20070117261
    Abstract: A multilayer printed wiring board includes a flexible portion that is constituted from a flexible base material in which an inner layer circuit pattern has been formed, and a hard portion that is constituted from a hard base material that is layered on a portion of the flexible base material via an adhesive layer and in which an outer layer circuit pattern has been formed. The border of the flexible portion and the hard portion is covered by a covering layer that continuously covers the flexible base material and the hard base material, with an exposed portion of the inner layer circuit pattern being exposed. A plating layer is formed by performing surface treatment (plating) for the exposed portion and the outer layer circuit pattern.
    Type: Application
    Filed: November 9, 2006
    Publication date: May 24, 2007
    Inventors: Yukihiro Ueno, Yuhji Takamoto
  • Publication number: 20070089826
    Abstract: A method for producing a multilayer printed wiring board includes an inner layer formation step of forming an inner layer pattern in a core substrate divided corresponding to a flexible portion that is made bendable and a hard portion that is made rigid, and an outer layer formation step of forming an outer layer such that an outer layer material that covers the core substrate is caused to make contact at the hard portion, and an outer layer pattern formation step of forming an outer layer pattern in the surface of the outer layer material, and a removal step of removing a covering portion that is the outer layer material and is covering the flexible portion, and an outer shape formation step of forming the outer shape of a layered substrate formed via the removal step.
    Type: Application
    Filed: October 16, 2006
    Publication date: April 26, 2007
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yukihiro Ueno, Yuhji Takamoto
  • Patent number: 7199329
    Abstract: A semiconductor part 1 in which a metal terminal 2 is formed on its back surface and side surface is mounted so that only the back surface portion of the metal terminal 2 is in contact with a cream solder 3. When the side surface portion of the metal terminal 2 is irradiated with laser beams, the back surface portion of the metal terminal 2 is heated by thermal conduction from the side surface portion to the back surface portion of the metal terminal 2 and the cream solder 3 in contact with the back surface portion of the metal terminal 2 is melted, whereby soldering is performed.
    Type: Grant
    Filed: August 10, 2004
    Date of Patent: April 3, 2007
    Assignee: Niigata Seimitsu Co., Ltd.
    Inventors: Akihiro Mano, Yukihiro Ueno, Hironori Urasawa, Yuki Oishi, Tadashi Miyazaki
  • Publication number: 20070063355
    Abstract: In a multilayer circuit board of the present invention, a plurality of circuit substrates configured by forming a circuit pattern on an insulating base material are stacked via an insulating layer, a through-hole and a via hole are formed in the layering direction, and laser processability and laser processing speed for a processing laser beam used in formation of the through-hole and the via hole are about the same for the insulating substrate material and the insulating layer.
    Type: Application
    Filed: June 6, 2006
    Publication date: March 22, 2007
    Inventors: Yukihiro Ueno, Keijiroh Edo
  • Publication number: 20070034596
    Abstract: The present invention is configured such that a wiring pattern, formed by forming an etching resist on metal foil that has been layered on an insulating resin board and performing etching via this etching resist, is provided with a circuit pattern constituting an electronic circuit and a dummy pattern provided in the vicinity of and separated from the circuit pattern, such that side etching of the circuit pattern is suppressed by mitigating the rate at which etching advances for the circuit pattern.
    Type: Application
    Filed: August 9, 2006
    Publication date: February 15, 2007
    Inventors: Yukihiro Ueno, Noboru Okabayashi
  • Publication number: 20070017698
    Abstract: An inner printed wiring board is provided with an inner insulating resin layer, an inner circuit pattern, and an inner via land. In order for the inner via land to make an interlayer connection, a pattern form for making a connection, unlike an ordinary wiring pattern, is adopted. The inner circuit pattern is formed with the same formation method and form as an ordinarily formed wiring pattern. The inner via land adopts a form having an inner window portion in which an inner conducting layer was removed during formation.
    Type: Application
    Filed: July 18, 2006
    Publication date: January 25, 2007
    Inventor: Yukihiro Ueno
  • Publication number: 20060157270
    Abstract: A printed wiring substrate has a circuit wiring area that has a circuit wiring pattern formed thereon and a peripheral area that is placed in the periphery of the circuit wiring area. The peripheral area has a property display area that is provided with a display location specified in association with a property for displaying a property of the printed wiring substrate. The property can be something that indicates an attribute of the printed wiring substrate such as production lot information, information on an inspection result of an electrical property (such as short-circuit defect, disconnection defect and wiring resistance defect), information on a visual inspection result (such as plating defect and silk screen defect), and the like.
    Type: Application
    Filed: January 11, 2006
    Publication date: July 20, 2006
    Inventor: Yukihiro Ueno
  • Publication number: 20060108145
    Abstract: An insulating resin layer 50 is formed on a surface of a conductor portion 2 by performing a plating pretreatment to the conductor portion 2 that has been formed on a surface of a wiring board substrate 1, and forming numerous dendrites 3 on the surface of the conductor portion 2 using an electroplating or chemical plating method. The insulating resin layer 50 is then formed by stacking an insulating resin plate 50 that has a semi-cured adhesive layer 40 formed thereon in advance on the conductor portion 2 and the dendrites 3, and then applying pressure and raising temperature for laminate bonding.
    Type: Application
    Filed: November 17, 2005
    Publication date: May 25, 2006
    Inventor: Yukihiro Ueno
  • Publication number: 20060086535
    Abstract: A plating resist film 2 is formed on a wiring board substrate 1 as a core material of a multilayer printed wiring board, then a through-hole 3 is formed, and through-hole conductor 4 is formed along the wall surface of the through-hole 3 and the through-hole surface of the plating resist film 2, so that protrusion portion 4a is formed in the through-hole conductor 4. The plating resist film 2 is then stripped off and a panel plating layer 5 is formed on the surface of the wiring board substrate 1 and the through-hole conductor 4 so that the through-hole 4 and the panel plating layer 5 are connected with the protrusion 4a coated, and thus the connection area can be increased.
    Type: Application
    Filed: October 26, 2005
    Publication date: April 27, 2006
    Inventor: Yukihiro Ueno