Patents by Inventor Yukihiro Ushiku

Yukihiro Ushiku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7831330
    Abstract: A process control system includes a client computer which prepares a correlation between a reference monitored value of apparatus information and a feature quantity, a manufacturing execution system which prepares a processing recipe describing, as a first setting value in an actual manufacturing process, a value of the control parameter, an apparatus information collection section which collects an objective monitored value of the apparatus information in operation of the actual manufacturing process with the first setting value, a feature quantity calculation section which calculates a value of a feature quantity corresponding to the objective monitored value based on the correlation, a parameter calculation section which calculates a second setting value in the actual manufacturing process on the basis of the value of the feature quantity, and an apparatus control unit which changes the processing recipe with the second setting value being as a setting value of the second step.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: November 9, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junji Sugamoto, Yukihiro Ushiku, Kazutaka Akiyama, Shoichi Harakawa
  • Patent number: 7702413
    Abstract: The present invention provides a solution for interleaving data frames, in a semiconductor device manufacturing system in which the processing apparatus for conducting a process on any one of a semiconductor substrate and a thin film on a surface thereof; a self-diagnostic system for diagnosing a state of the processing apparatus; and a parameter fitting apparatus for maintaining a parameter of the self-diagnostic system when an inspection result of the semiconductor substrate having undergone the process has been determined to be correct, and for changing the parameter of the self-diagnostic system when the inspection result has been determined to be incorrect.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: April 20, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukihiro Ushiku, Akira Ogawa, Hidenori Kakinuma, Shunji Shuto, Masahiro Abe, Tatsuo Akiyama, Shigeru Komatsu
  • Patent number: 7700381
    Abstract: A semiconductor wafer has a bevel contour formed along the periphery thereof, products formed on the wafer, and an ID mark formed on the bevel contour. The ID mark shows at least the properties, manufacturing conditions, and test results of the products.
    Type: Grant
    Filed: February 9, 2006
    Date of Patent: April 20, 2010
    Assignee: Kabushikia Kaisha Toshiba
    Inventors: Tsunetoshi Arikado, Masao Iwase, Soichi Nadahara, Yuso Udo, Yukihiro Ushiku, Shinichi Nitta, Moriya Miyashita, Junji Sugamoto, Hiroaki Yamada, Hajime Nagano, Katsujiro Tanzawa, Hiroshi Matsushita, Norihiko Tsuchiya, Katsuya Okumura
  • Patent number: 7623937
    Abstract: The present invention provides a solution for interleaving data frames, in a semiconductor device manufacturing system in which the processing apparatus for conducting a process on any one of a semiconductor substrate and a thin film on a surface thereof; a self-diagnostic system for diagnosing a state of the processing apparatus; and a parameter fitting apparatus for maintaining a parameter of the self-diagnostic system when an inspection result of the semiconductor substrate having undergone the process has been determined to be correct, and for changing the parameter of the self-diagnostic system when the inspection result has been determined to be incorrect.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: November 24, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukihiro Ushiku, Akira Ogawa, Hidenori Kakinuma, Shunji Shuto, Masahiro Abe, Tatsuo Akiyama, Shigeru Komatsu
  • Publication number: 20090276078
    Abstract: A process control system includes a client computer which prepares a correlation between a reference monitored value of apparatus information and a feature quantity, a manufacturing execution system which prepares a processing recipe describing, as a first setting value in an actual manufacturing process, a value of the control parameter, an apparatus information collection section which collects an objective monitored value of the apparatus information in operation of the actual manufacturing process with the first setting value, a feature quantity calculation section which calculates a value of a feature quantity corresponding to the objective monitored value based on the correlation, a parameter calculation section which calculates a second setting value in the actual manufacturing process on the basis of the value of the feature quantity, and an apparatus control unit which changes the processing recipe with the second setting value being as a setting value of the second step.
    Type: Application
    Filed: July 10, 2009
    Publication date: November 5, 2009
    Inventors: Junji Sugamoto, Yukihiro Ushiku, Kazutaka Akiyama, Shoichi Harakawa
  • Patent number: 7596421
    Abstract: A process control system includes a client computer which prepares a correlation between a reference monitored value of apparatus information and a feature quantity, a manufacturing execution system which prepares a processing recipe describing, as a first setting value in an actual manufacturing process, a value of the control parameter, an apparatus information collection section which collects an objective monitored value of the apparatus information in operation of the actual manufacturing process with the first setting value, a feature quantity calculation section which calculates a value of a feature quantity corresponding to the objective monitored value based on the correlation, a parameter calculation section which calculates a second setting value in the actual manufacturing process on the basis of the value of the feature quantity, and an apparatus control unit which changes the processing recipe with the second setting value being as a setting value of the second step.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: September 29, 2009
    Assignee: Kabushik Kaisha Toshiba
    Inventors: Junji Sugamoto, Yukihiro Ushiku, Kazutaka Akiyama, Shoichi Harakawa
  • Patent number: 7588973
    Abstract: In a semiconductor device having a semiconductor element having a plurality of SOI-Si layers, the height of element isolation regions from the surface of the semiconductor substrate are substantially equal to each other. Alternatively, the element isolation regions are formed at the equal height on the semiconductor substrate and then a plurality of SOI-Si layers appropriately different in thickness are formed. In this manner, it is possible to obtain element isolation regions having substantially the same height from the semiconductor substrate and desired element regions having SOI-Si layers different in height. The thickness of a single crystalline silicon film (SOI-Si layer) may be appropriately changed by another method which includes depositing an amorphous silicon film and applying a heat processing to form an epi layer, and removing an unnecessary portion.
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: September 15, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yukihiro Ushiku
  • Patent number: 7531462
    Abstract: A method of inspecting a semiconductor wafer, comprises removing a device structure film on the semiconductor wafer with a chemical solution to expose a crystal surface of the semiconductor wafer; coating a protected area, which is a part of the crystal surface of the semiconductor wafer, with a mask material for protecting the crystal surface of the semiconductor wafer; etching the semiconductor wafer selectively, thereby making a crystal defect in a non-protected area, which is a part of the crystal surface of the semiconductor wafer that is not coated with the mask material, appear after the crystal surface is coated with the mask material; removing the mask material after the selective etching; carrying out quantitative measurement of the protected area and the non-protected area using an optical defect inspection apparatus or a beam-type defect inspection apparatus; and calculating the number of crystal defects of the semiconductor wafer base on the result of the measurement.
    Type: Grant
    Filed: June 1, 2006
    Date of Patent: May 12, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsujiro Tanzawa, Norihiko Tsuchiya, Junji Sugamoto, Yukihiro Ushiku
  • Patent number: 7529634
    Abstract: A method of searching for clustering faults is employed for semiconductor device manufacturing. The method enters data on faults present in a search target, calculates a frequency distribution of the faults in unit cells divided from the search target, approximates the frequency distribution by overlaying at least two discrete distribution functions, and searches for clustering faults according to weights of the discrete distribution functions on the frequency distribution.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: May 5, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kunihiro Mitsutake, Yukihiro Ushiku
  • Patent number: 7463941
    Abstract: A quality control system has: a QC value storage unit, a data acquisition device, a device internal information storage unit, a recipe storage unit, a QC value prediction unit, a wafer determination unit, a recipe selection unit, and a measurement device.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: December 9, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Ogawa, Yukihiro Ushiku, Tomomi Ino
  • Patent number: 7413914
    Abstract: A process of manufacturing a semiconductor device utilizing a thermo-chemical reaction is started based on preset initial settings, a state function of an atmosphere associated with the thermo-chemical reaction is measured, a state of the atmosphere and a change thereof are analyzed based on measurement data obtained by the measurement, and then, analysis data obtained by the analysis is fed back to a manufacturing process.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: August 19, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukihiro Ushiku, Mitsutoshi Nakamura
  • Patent number: 7361960
    Abstract: A first insulator film and a first polysilicon film are formed on first and second element regions of a semiconductor substrate. The first insulator film and first polysilicon film are removed from the second element region. A second insulator film is formed on the second element region from which the first insulator film and first polysilicon film are removed, and a second polysilicon film is formed on the second insulator film. The first polysilicon film is processed, forming a first gate electrode at the first element region. The second polysilicon film is processed, forming a second gate electrode at the second element region. A silicon nitride film is removed from an element-isolation region. A metal film is formed on the region from which the silicon nitride film has been removed, and connects the first and second gate electrodes.
    Type: Grant
    Filed: October 17, 2000
    Date of Patent: April 22, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshitaka Tsunashima, Kiyotaka Miyano, Yukihiro Ushiku
  • Patent number: 7324855
    Abstract: A process-state management system encompasses: a plurality of production machines; a control server configured to collectively control at least part of the production machines; a management server including a data-linking module configured to link operation-management data of the production machines with corresponding management information transmitted from the control server, respectively, the management server analyze the operation-management data linked with the management information with a common analysis application; and a management database configured to store the operation-management data linked with the management information.
    Type: Grant
    Filed: September 2, 2005
    Date of Patent: January 29, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukihiro Ushiku, Hidenori Kakinuma, Tsutomu Miki, Junji Sugamoto, Akira Ogawa, Yoshinori Ookawauchi, Giichi Inoue, Tomomi Ino
  • Patent number: 7314766
    Abstract: A treatment method of a semiconductor wafer includes treating the semiconductor wafer in a first solution having at least one kind of an oxidative acid and an oxidizing agent and treating the semiconductor wafer in a second solution having at least one of HF and NH4F.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: January 1, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junji Sugamoto, Norihiko Tsuchiya, Yukihiro Ushiku, Katsujiro Tanzawa
  • Patent number: 7221991
    Abstract: A control system for a manufacturing apparatus includes manufacturing information input unit acquiring time series data of apparatus parameters controlling manufacturing apparatuses; failure pattern classification module classifying in-plane distributions of failures of each of the wafers into failure patterns; an index calculation unit configured to statistically process the time series data by algorithms to calculate indices corresponding to the respective algorithms; an index analysis unit providing first and second frequency distributions of the indices categorized with and without the target failure pattern, to implement significance test between the first and second frequency distributions; and an abnormal parameter extraction unit extracting failure cause index of failure pattern by comparing value of the significance test with test reference value.
    Type: Grant
    Filed: March 2, 2005
    Date of Patent: May 22, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Matsushita, Tomonobu Noda, Kenichi Kadota, Junji Sugamoto, Yukihiro Ushiku
  • Patent number: 7222026
    Abstract: An equipment for detecting faults in semiconductor integrated circuits includes a fault input unit to input fault information for the integrated circuits formed on a semiconductor wafer, a superimposing unit to superimpose the fault information with repeating units within the surface of the semiconductor wafer, and a first characteristic factor calculation unit to calculate a first characteristic factor showing a degree to which faults are repeated every repeating unit.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: May 22, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Matsushita, Kunihiro Mitsutake, Yukihiro Ushiku
  • Patent number: 7188049
    Abstract: A control system for a manufacturing process includes an inspection tool inspecting a dislocation image in semiconductor substrate processed by manufacturing processes; an inspection information input module configured to acquire the inspected dislocation image; a process condition input module acquiring process conditions of the manufacturing processes; a structure information input module acquiring structure of the semiconductor substrate processed by target manufacturing process; a stress analysis module calculating stresses at nodes provided in the structure, based on target process condition and the structure; an origin setting module providing origins at positions where stress concentration having stress value not less than reference value is predicted; a dislocation dynamics analysis module calculating dislocation pattern in stress field for each position of the origins; and a dislocation pattern comparison module comparing the dislocation pattern with the inspected dislocation image so as to determine
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: March 6, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Norihiko Tsuchiya, Yukihiro Ushiku
  • Publication number: 20060287754
    Abstract: A process control system includes a client computer which prepares a correlation between a reference monitored value of apparatus information and a feature quantity, a manufacturing execution system which prepares a processing recipe describing, as a first setting value in an actual manufacturing process, a value of the control parameter, an apparatus information collection section which collects an objective monitored value of the apparatus information in operation of the actual manufacturing process with the first setting value, a feature quantity calculation section which calculates a value of a feature quantity corresponding to the objective monitored value based on the correlation, a parameter calculation section which calculates a second setting value in the actual manufacturing process on the basis of the value of the feature quantity, and an apparatus control unit which changes the processing recipe with the second setting value being as a setting value of the second step.
    Type: Application
    Filed: June 21, 2006
    Publication date: December 21, 2006
    Inventors: Junji Sugamoto, Yukihiro Ushiku, Kazutaka Akiyama, Shoichi Harakawa
  • Publication number: 20060281281
    Abstract: A method of inspecting a semiconductor wafer, comprises removing a device structure film on the semiconductor wafer with a chemical solution to expose a crystal surface of the semiconductor wafer; coating a protected area, which is a part of the crystal surface of the semiconductor wafer, with a mask material for protecting the crystal surface of the semiconductor wafer; etching the semiconductor wafer selectively, thereby making a crystal defect in a non-protected area, which is a part of the crystal surface of the semiconductor wafer that is not coated with the mask material, appear after the crystal surface is coated with the mask material; removing the mask material after the selective etching; carrying out quantitative measurement of the protected area and the non-protected area using an optical defect inspection apparatus or a beam-type defect inspection apparatus; and calculating the number of crystal defects of the semiconductor wafer base on the result of the measurement.
    Type: Application
    Filed: June 1, 2006
    Publication date: December 14, 2006
    Inventors: Katsujiro Tanzawa, Norihiko Tsuchiya, Junji Sugamoto, Yukihiro Ushiku
  • Publication number: 20060235560
    Abstract: A quality control system has: a QC value storage unit that stores QC actual measurements of past lots, a data acquisition device that acquires the device internal information of a processing device processing an intended lot, a device internal information storage unit that stores the device internal information, a recipe storage unit that stores a plurality of recipes classified by the distribution of sampling density within a wafer, a QC value prediction unit that predicts a QC prediction value of the intended lot using the device internal information and the QC actual measurements, a wafer determination unit that determines a sample wafer to be measured from among a plurality of wafers constituting the intended lot using the QC prediction value, a recipe selection unit that selects an application recipe to be applied to the sample wafer from among the plurality of recipes using the QC prediction value, and a measurement device that makes a QC measurement on the sample wafer using the application recipe and
    Type: Application
    Filed: April 3, 2006
    Publication date: October 19, 2006
    Inventors: Akira Ogawa, Yukihiro Ushiku, Tomomi Ino