Patents by Inventor Yukihiro Ushiku
Yukihiro Ushiku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20030003608Abstract: A semiconductor wafer has a bevel contour formed along the periphery thereof, products formed on the wafer, and an ID mark formed on the bevel contour. The ID mark shows at least the properties, manufacturing conditions, and test results of the products.Type: ApplicationFiled: March 20, 2002Publication date: January 2, 2003Inventors: Tsunetoshi Arikado, Masao Iwase, Soichi Nadahara, Yuso Udo, Yukihiro Ushiku, Shinichi Nitta, Moriya Miyashita, Junji Sugamoto, Hiroaki Yamada, Hajime Nagano, Katsujiro Tanzawa, Hiroshi Matsushita, Norihiko Tsuchiya, Katsuya Okumura
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Publication number: 20020193891Abstract: The sensor signals relating to the equipment are input from the sensors. The scalar distances of the recognition spaces of every combination of the sensor signals are computed. The flag signals of every combination of the sensor signals are outputted according to whether or not the scalar distances are included in the normal ranges of the recognition spaces. The failures of the equipment are determined according to the flag signals.Type: ApplicationFiled: March 26, 2002Publication date: December 19, 2002Inventor: Yukihiro Ushiku
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Publication number: 20020180449Abstract: A process of manufacturing a semiconductor device utilizing a thermo-chemical reaction is started based on preset initial settings, a state function of an atmosphere associated with the thermo-chemical reaction is measured, a state of the atmosphere and a change thereof are analyzed based on measurement data obtained by the measurement, and then, analysis data obtained by the analysis is fed back to a manufacturing process.Type: ApplicationFiled: March 29, 2002Publication date: December 5, 2002Applicant: Kabushiki Kaisha ToshibaInventors: Yukihiro Ushiku, Mitsutoshi Nakamura
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Publication number: 20020053065Abstract: A method of searching for clustering faults is employed for semiconductor device manufacturing, The method enters data on faults present in a search target, calculates a frequency distribution of the faults in unit cells divided from the search target, approximates the frequency distribution by overlaying at least two discrete distribution functions, and searches for clustering faults according to weights of the discrete distribution functions on the frequency distribution.Type: ApplicationFiled: August 20, 2001Publication date: May 2, 2002Inventors: Kunihiro Mitsutake, Yukihiro Ushiku
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Patent number: 6184083Abstract: A first insulator film and a first polysilicon film are formed on first and second element regions of a semiconductor substrate. The first insulator film and first polysilicon film are removed from the second element region. A second insulator film is formed on the second element region from which the first insulator film and first polysilicon film are removed, and a second polysilicon film is formed on the second insulator film. The first polysilicon film is processed, forming a first gate electrode at the first element region. The second polysilicon film is processed, forming a second gate electrode at the second element region. A silicon nitride film is removed from an element-isolation region. A metal film is formed on the region from which the silicon nitride film has been removed, and connects the first and second gate electrodes.Type: GrantFiled: June 29, 1998Date of Patent: February 6, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Yoshitaka Tsunashima, Kiyotaka Miyano, Yukihiro Ushiku
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Patent number: 5903027Abstract: A MOS type semiconductor device has a gate whose length is 170 nm (0.17 .mu.m) or less, a junction depth of source and drain diffusion layers in the vicinity of a channel is 22 nm or less, and a concentration of impurities at the surface in the source and drain diffusion layers is made to 10.sup.20 cm.sup.-3 or more. Such structure is obtained using solid phase diffusion using heat range from 950.degree. C. to 1050.degree. C. and/or narrowing gate width by ashing or etching. The other MOS type semiconductor device is characterized in that the relationship between the junction depth x.sub.j ?nm! in the source and drain diffusion layer regions and the effective channel length L.sub.eff ?nm! is determined by L.sub.eff >0.69 x.sub.j -6.17.Type: GrantFiled: August 13, 1997Date of Patent: May 11, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yoshitomi, Masanobu Saito, Hisayo Momose, Hiroshi Iwai, Yukihiro Ushiku, Mizuki Ono, Yasushi Akasaka, Hideaki Nii, Satoshi Matsuda, Yasuhiro Katsumata, Tatsuya Ooguro, Claudio Fiegna
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Patent number: 5898203Abstract: A diffused server as a source and a drain. It is formed comprised of a deep first diffused layer and a shallow second diffused layer positioned between the first diffused layer and the channel region. In the second diffused region, a distribution in a depth direction of carriers has a profile in which the concentration is more than 5.times.10.sup.18 cm-.sup.-3 at the peak and is in correspondence with a carrier concentration of the semiconductor substrate at a depth less than 0.04 .mu.m. Since the second diffused layer has a high concentration, the short-channel effect can be suppressed. As the second diffused region, a solid phase diffusion source such as an impurity doped silicate glass is used.Type: GrantFiled: July 30, 1997Date of Patent: April 27, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yoshitomi, Masanobu Saito, Hisayo Momose, Hiroshi Iwai, Yukihiro Ushiku, Mizuki Ono, Yasushi Akasaka, Hideaki Nii, Satoshi Matsuda, Yasuhiro Katsumata
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Patent number: 5844278Abstract: The present invention provides a semiconductor device which includes a substrate having a projection-shaped semiconductor element region, a gate electrode formed through a gate insulating film on the upper face and side face of the element region, and a first conductivity type source region and drain region provided in a manner to form a channel region on the upper face of the element region across the gate electrode, and which has a high concentration impurity region containing a second conductivity type impurity at a concentration higher than that on the surface of the channel region in the central part of the projection-shaped semiconductor element region.Type: GrantFiled: September 13, 1995Date of Patent: December 1, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Tomohisa Mizuno, Yukihiro Ushiku, Makoto Yoshimi, Mamoru Terauchi, Shigeru Kawanaka
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Patent number: 5766965Abstract: A diffused layer serves as a source and a drain. It is formed comprised of a deep first diffused layer and a shallow second diffused layer positioned between the first diffused layer and the channel region. In the second diffused region, a distribution in a depth direction of carriers has a profile in which the concentration is more than 5.times.10.sup.18 cm.sup.-3 at the peak and is in correspondence with a carrier concentration of the semiconductor substrate at a depth less than 0.04 .mu.m. Since the second diffused layer has a high concentration, the short-channel effect can be suppressed. As the second diffused region, a solid phase diffusion source such as an impurity doped silicate glass is used.Type: GrantFiled: December 5, 1994Date of Patent: June 16, 1998Inventors: Takashi Yoshitomi, Masanobu Saito, Hisayo Momose, Hiroshi Iwai, Yukihiro Ushiku, Mizuki Ono, Yasushi Akasaka, Hideaki Nii, Satoshi Matsuda, Yasuhiro Katsumata
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Patent number: 5763953Abstract: A semiconductor device includes a first metal film formed on a semiconductor substrate, a second metal film formed on the first metal film and containing silver as a main component, and a protective film containing a metal element of the first metal film and covering at least the upper surface of the second metal film. The protective film is formed by annealing in an atmosphere containing a predetermined element. That is, the metal element of the first metal film is diffused into the second metal film and reacts with the predetermined element in the atmosphere on the surface of the second metal film, thereby forming the protective film. Aggregation of silver is prevented in the presence of the protective film.Type: GrantFiled: January 18, 1996Date of Patent: June 9, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Tadashi IIjima, Hisako Ono, Yukihiro Ushiku, Akira Nishiyama, Naomi Nakasa
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Patent number: 5739575Abstract: Element isolation technique for LSIs having a fine pattern of sub-micron class or finer. A high strained region doped with impurities at a high concentration is formed under, and remote from, a buried insulating material (dielectrics) layer for element isolation. With this buried dielectrics element isolation (BDEI) structure, since the high strained layer exists just under the buried dielectrics layer, crystal defects generated near the buried dielectrics layer due to strain caused by a difference of thermal expansion coefficient between a semiconductor layer and the buried dielectrics layer, are moved toward the high strained layer. Accordingly, the crystal defects do not reach an active region where active elements are formed, so that leakage current in the p-n junction formed in the active layer can be advantageously reduced.Type: GrantFiled: August 30, 1996Date of Patent: April 14, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Masanori Numano, Norihiko Tsuchiya, Hiroyasu Kubota, Yoshiaki Matsushita, Yoshiki Hayashi, Yukihiro Ushiku, Atsushi Yagishita, Satoshi Inaba, Yasunori Okayama, Minoru Takahashi
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Patent number: 5698881Abstract: A MOS type semiconductor device has a gate whose length is 170 nm (0.17 .mu.m) or less, a junction depth of source and drain diffusion layers in the vicinity of a channel is 22 nm or less, and a concentration of impurities at the surface in the source and drain diffusion layers is made to 10.sup.20 cm.sup.-3 or more. Such structure is obtained using solid phase diffusion using heat range from 950.degree. C. to 1050.degree. C. and/or narrowing gate width by ashing or etching. The other MOS type semiconductor device is characterized in that the relationship between the junction depth x.sub.j ?nm! in the source and drain diffusion layer regions and the effective channel length L.sub.eff ?nm! is determined by L.sub.eff >0.69 x.sub.j -6.17.Type: GrantFiled: December 2, 1994Date of Patent: December 16, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yoshitomi, Masanobu Saito, Hisayo Momose, Hiroshi Iwai, Yukihiro Ushiku, Mizuki Ono, Yasushi Akasaka, Hideaki Nii, Satoshi Matsuda, Yasuhiro Katsumata, Tatsuya Ooguro, Claudio Fiegna
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Patent number: 5675176Abstract: A semiconductor device has a semiconductor substrate having a groove, and a semiconductor element formed in a surface region of the semiconductor substrate. A substance having a thermal expansion coefficient different from the semiconductor substrate is embedded in at least a portion of the groove, a crystal defect is generated from the region near the bottom of the groove in the semiconductor substrate, thereby alleviating stress and strain in other regions of the semiconductor substrate, such that such regions cannot generate crystal defects in a region necessary for a circuit operation of the semiconductor element of the surface region.Type: GrantFiled: September 15, 1995Date of Patent: October 7, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Yukihiro Ushiku, Atsushi Yagishita, Satoshi Inaba, Minoru Takahashi, Masanori Numano, Yoshiki Hayashi, Yoshiaki Matsushita, Yasunori Okayama, Hiroyasu Kubota, Norihiko Tsuchiya
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Patent number: 5529954Abstract: A semiconductor device includes a first metal film formed on a semiconductor substrate, a second metal film formed on the first metal film and containing silver as a main component, and a protective film containing a metal element of the first metal film and covering at least the upper surface of the second metal film. The protective film is formed by annealing in an atmosphere containing a predetermined element. That is, the metal element of the first metal film is diffused into the second metal film and reacts with the predetermined element in the atmosphere on the surface of the second metal film, thereby forming the protective film. Aggregation of silver is prevented in the presence of the protective film.Type: GrantFiled: June 7, 1995Date of Patent: June 25, 1996Assignee: Kabushiki Kaisha ToshibaInventors: Tadashi Iijima, Hisako Ono, Yukihiro Ushiku, Akira Nishiyama, Naomi Nakasa
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Patent number: 5434440Abstract: A diffused layer serves as a source and a drain. It is formed comprised of a deep first diffused layer and a shallow second diffused layer positioned between the first diffused layer and the channel region. In the second diffused region, a distribution in a depth direction of carriers has a profile in which the concentration is more than 5.times.10.sup.18 cm.sup.-3 at the peak and is in correspondence with a carrier concentration of the semiconductor substrate at a depth less than 0.04 .mu.m. Since the second diffused layer has a high concentration, the short-channel effect can be suppressed. As the second diffused region, a solid phase diffusion source such as an impurity doped silicate glass is used.Type: GrantFiled: May 28, 1993Date of Patent: July 18, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yoshitomi, Masanobu Saito, Hisayo Momose, Hiroshi Iwai, Yukihiro Ushiku, Mizuki Ono, Yasushi Akasaka, Hideaki Nii, Satoshi Matsuda, Yasuhiro Katsumata
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Patent number: 5185279Abstract: A method of manufacturing an insulated-gate type field effect transistor includes the steps of forming an insulating film, on a semiconductor substrate, forming a first polycrystalline silicon layer on the insulating film, forming a second polycrystalline silicon layer on the frist polycrystalline silicon layer, patterning the first and second polycrystalline silicon layers to form a gate electrode and a masking layer, doping an impurity of a first conductivity type in the semiconductor substrate using the gate electrode and the masking layer as masks, thereby forming a source region and a drain region, starting etching the masking layer, detecting a natural oxide film on the gate electrode, stopping the etching, and ion-implanting an impurity of a second conductivity type in a region of the semiconductor substrate under the gate electrode through the gate electrode, thereby forming a channel-doped region.Type: GrantFiled: March 22, 1991Date of Patent: February 9, 1993Assignee: Kabushiki Kaisha ToshibaInventor: Yukihiro Ushiku
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Patent number: 5032890Abstract: A semiconductor integrated circuit device including a semiconductor substrate, a lower interconnection layer pattern formed along first parallel lines on the substrate, an insulating layer formed on the pattern, and an upper interconnection layer pattern formed along second parallel lines perpendicularly intersecting with the first parallel lines on the insulating layer. A dummy pattern made of the same material as that of the lower interconnection layer pattern, and not electrically connected to the upper and lower interconnection layer patterns, is formed in a region which is arranged below the upper interconnection layer pattern and in which the first parallel lines intersect the second parallel lines. The dummy pattern has the same level as that of the lower interconnection layer pattern, has no lower interconnection layer pattern, and is adjacent to the lower interconnection layer pattern, at a predetermined interval from the lower interconnection layer pattern.Type: GrantFiled: January 30, 1989Date of Patent: July 16, 1991Assignee: Kabushiki Kaisha ToshibaInventors: Yukihiro Ushiku, Takashi Mitsuhashi
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Patent number: 5028552Abstract: A method of manufacturing an insulated-gate type field effect transistor includes the steps of forming an insulating film, on a semiconductor substrate, forming a polycrystalline silicon layer on the insulating film, forming a masking layer on the polycrystalline silicon layer, patterning the polycrystalline silicon and masking layers to form a gate electrode and a masking layer, doping an impurity of a first conductivity type in the semiconductor substrate using the gate electrode and the masking layer as masks, thereby forming a source region and a drain region, removing the masking layer, and ion-implanting an impurity of a second conductivity type in a region of the semiconductor substrate under the gate electrode through the gate electrode, thereby forming a channel-doped region. In this method, after the source and drain regions are formed, the impurity of the second conductivity type is ion-implanted in the substrate through the thin gate electrode to form the channel-doped region.Type: GrantFiled: August 17, 1989Date of Patent: July 2, 1991Assignee: Kabushiki Kaisha ToshibaInventor: Yukihiro Ushiku
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Patent number: 4661721Abstract: A semiconductor integrated circuit device wherein a plurality of clock signal lines provided with a clock signal are drawn out independently from the respective output terminals of a plurality of divided clock drivers, the clock signal lines being connected together by a common connecting line.Type: GrantFiled: August 21, 1985Date of Patent: April 28, 1987Assignee: Kabushiki Kaisha ToshibaInventor: Yukihiro Ushiku
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Patent number: 4587549Abstract: A multilayer interconnection structure for a semiconductor device has interconnection layers superposed on each other on the surface of a semiconductor substrate with an insulating layer interposed therebetween. Connection between the desired interconnection layers or between the desired interconnection layer and semiconductor substrate is effected by means of a contact hole formed in the respective insulating layers. Two upper and lower interconnection layers intersect each other above the contact holes, and the contact hole does not overlap part of the traverse region of the upper interconnection layer in the intersecting section.Type: GrantFiled: April 7, 1983Date of Patent: May 6, 1986Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventor: Yukihiro Ushiku