Patents by Inventor Yukimasa Minami
Yukimasa Minami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10355077Abstract: In an ESD protection element configured to protect a semiconductor device, a first N-type low concentration diffusion layer is formed, as an offset layer for easing electric field concentration, under a LOCOS oxide film formed at each end of the gate electrode, and a second N-type low concentration diffusion layer and a third low concentration diffusion layer are formed under an N-type high concentration diffusion layer on the drain side to set the point of breakdown at a level deep inside a substrate from a surface of the substrate. The hold voltage is thus raised to a voltage equal to or higher than the operating voltage and a noise can be relieved without increasing the element size of the ESD protection element even when the noise having a large amount of positive electric charge is applied to a Vdd supply terminal.Type: GrantFiled: September 26, 2017Date of Patent: July 16, 2019Assignee: ABLIC INC.Inventor: Yukimasa Minami
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Patent number: 10205031Abstract: All resistors configuring a resistance voltage dividing circuit are formed by alternately arranging an N-type polycrystalline silicon and a P-type polycrystalline silicon and connecting the same in parallel or in series. The respective resistors themselves cancel a stress received from a resin upon packaging of the resistance voltage dividing circuit since the N-type polycrystalline silicon and the P-type polycrystalline silicon respectively indicate a shift amount in a reverse direction with respect to a stress. There can hence be provided a resistance voltage dividing circuit in which a variation in voltage division ratio at packaging is reduced than before.Type: GrantFiled: March 27, 2018Date of Patent: February 12, 2019Assignee: ABLIC Inc.Inventor: Yukimasa Minami
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Publication number: 20180286990Abstract: All resistors configuring a resistance voltage dividing circuit are formed by alternately arranging an N-type polycrystalline silicon and a P-type polycrystalline silicon and connecting the same in parallel or in series. The respective resistors themselves cancel a stress received from a resin upon packaging of the resistance voltage dividing circuit since the N-type polycrystalline silicon and the P-type polycrystalline silicon respectively indicate a shift amount in a reverse direction with respect to a stress. There can hence be provided a resistance voltage dividing circuit in which a variation in voltage division ratio at packaging is reduced than before.Type: ApplicationFiled: March 27, 2018Publication date: October 4, 2018Inventor: Yukimasa MINAMI
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Publication number: 20180090563Abstract: In an ESD protection element configured to protect a semiconductor device, a first N-type low concentration diffusion layer is formed, as an offset layer for easing electric field concentration, under a LOCOS oxide film formed at each end of the gate electrode, and a second N-type low concentration diffusion layer and a third low concentration diffusion layer are formed under an N-type high concentration diffusion layer on the drain side to set the point of breakdown at a level deep inside a substrate from a surface of the substrate. The hold voltage is thus raised to a voltage equal to or higher than the operating voltage and a noise can be relieved without increasing the element size of the ESD protection element even when the noise having a large amount of positive electric charge is applied to a Vdd supply terminal.Type: ApplicationFiled: September 26, 2017Publication date: March 29, 2018Inventor: Yukimasa MINAMI
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Patent number: 9793215Abstract: A semiconductor integratd circuit device includes fuse elements formed on an element isolation insulating film, and an insulating film, an interlayer insulating film and a silicon nitride film successively formed over the fuse elements. An opening region extends through the silicon nitride film into the interlayer insulating film above the fuse elements, and openings formed in the interlayer insulating film are positioned on both sides of middle portions of the fuse elements. The openings facilitate blowing off of the insulating film during laser cutting of the fuse elements, reducing physical damage to the element isolation insulating film under the fuse elements.Type: GrantFiled: April 26, 2016Date of Patent: October 17, 2017Assignee: SII Semiconductor CorporationInventor: Yukimasa Minami
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Patent number: 9704771Abstract: Provided is a flip-chip mounted semiconductor device in which a crack is less likely to develop. Flip chip mounting is carried out under the condition that no oxide film exists on the scribe region so as to eliminate the interface between the oxide film that remains on the scribe region and the silicon substrate from which a crack may develop. As a result, the circuit board, the encapsulant, and the silicon substrate are stacked at an end portion of the semiconductor chip.Type: GrantFiled: October 29, 2015Date of Patent: July 11, 2017Assignee: SII Semiconductor CorporationInventors: Yoichi Mimuro, Kotaro Watanabe, Yukimasa Minami
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Publication number: 20160322301Abstract: A BPSG film (104) arranged on fuse elements (103), an interlayer insulating film (105) for laminating metal wiring, and a silicon nitride film (106) formed thereon are selectively removed with a polyimide (107) being used as a mask to form an opening region (108) above the fuse elements (103). Formation of slits (201) between adjacent fuse elements (103) in the vicinity of both sides of each of middle portions of the fuse elements (103) in the opening region (108) at regular intervals facilitates blowing off of the insulating film during laser cutting of the fuse element (103), reducing physical damage to an element isolation insulating film (102) under the fuse elements (103) to prevent electrical connection with a silicon substrate (101).Type: ApplicationFiled: April 26, 2016Publication date: November 3, 2016Inventor: Yukimasa MINAMI
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Publication number: 20160126155Abstract: Provided is a flip-chip mounted semiconductor device in which a crack is less likely to develop. Flip chip mounting is carried out under the condition that no oxide film exists on the scribe region so as to eliminate the interface between the oxide film that remains on the scribe region and the silicon substrate from which a crack may develop. As a result, the circuit board, the encapsulant, and the silicon substrate are stacked at an end portion of the semiconductor chip.Type: ApplicationFiled: October 29, 2015Publication date: May 5, 2016Inventors: Yoichi MIMURO, Kotaro WATANABE, Yukimasa MINAMI
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Patent number: 9231101Abstract: A semiconductor device includes a semiconductor substrate, a body region, a body contact region and a cancelling region each of the first conductivity type, and a buried layer, an epitaxial layer and a source region each of the second conductivity type. A trench is provided in the epitaxial layer from a surface thereof. A gate insulating film is provided on an inner wall of the trench, and a gate electrode made of polycrystalline silicon is in contact with the gate insulating film and fills the trench. The cancelling region, which is provided below a bottom surface of the trench for cancelling a conductivity type of the buried layer, has a distribution center located below a boundary surface between the buried layer and the epitaxial layer. A trench bottom surface lower region of the first conductivity type is provided from the bottom surface of the trench continuously to the cancelling region.Type: GrantFiled: September 5, 2014Date of Patent: January 5, 2016Assignee: SEIKO INSTRUMENTS INC.Inventor: Yukimasa Minami
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Patent number: 8937365Abstract: In a semiconductor integrated circuit device including fuse elements for performing laser trimming processing, a dummy fuse formed of a first polycrystalline Si film is formed between the fuse elements formed of a second polycrystalline Si film, and a nitride film is formed on the dummy fuse. In this manner, the step difference of an interlayer film caused by the presence and absence of the fuse element formed of the polycrystalline Si film is eliminated, to thereby prevent SOG films having moisture-absorption characteristics on an inner surface of a fuse opening region and on an internal element side from connecting to each other.Type: GrantFiled: September 30, 2013Date of Patent: January 20, 2015Assignee: Seiko Instruments Inc.Inventor: Yukimasa Minami
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Publication number: 20140374821Abstract: Provided is a semiconductor device having a vertical MOS transistor and a method of manufacturing the same. The vertical MOS transistor has a trench gate, a distance between a gate electrode and an N-type high concentration buried layer below the gate electrode is formed longer than that in the conventional structure, and a P-type trench bottom surface lower region (5) is formed therebetween. In this manner, when a high voltage is applied to a drain region and 0 V is applied to the gate electrode, the trench bottom surface lower region (5) is depleted, thereby increasing the breakdown voltage in the OFF state.Type: ApplicationFiled: September 5, 2014Publication date: December 25, 2014Inventor: Yukimasa MINAMI
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Patent number: 8859369Abstract: Provided is a semiconductor device having a vertical MOS transistor and a method of manufacturing the same. The vertical MOS transistor has a trench gate, a distance between a gate electrode and an N-type high concentration buried layer below the gate electrode is formed longer than that in the conventional structure, and a P-type trench bottom surface lower region (5) is formed therebetween. In this manner, when a high voltage is applied to a drain region and 0 V is applied to the gate electrode, the trench bottom surface lower region (5) is depleted, thereby increasing the breakdown voltage in the OFF state.Type: GrantFiled: February 7, 2013Date of Patent: October 14, 2014Assignee: Seiko Instruments Inc.Inventor: Yukimasa Minami
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Publication number: 20140091425Abstract: In a semiconductor integrated circuit device including fuse elements for performing laser trimming processing, a dummy fuse formed of a first polycrystalline Si film is formed between the fuse elements formed of a second polycrystalline Si film, and a nitride film is formed on the dummy fuse. In this manner, the step difference of an interlayer film caused by the presence and absence of the fuse element formed of the polycrystalline Si film is eliminated, to thereby prevent SOG films having moisture-absorption characteristics on an inner surface of a fuse opening region and on an internal element side from connecting to each other.Type: ApplicationFiled: September 30, 2013Publication date: April 3, 2014Applicant: SEIKO INSTRUMENTS INC.Inventor: Yukimasa MINAMI
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Patent number: 8574974Abstract: Forming a photoresist on a region other than a region on a trench gate electrode for a mask, a third gate insulating film on the trench gate electrode is etched and removed. After that, a non-doped polycrystalline silicon layer is formed on second and third gate insulating films and also on the trench gate electrode, and, N-type and P-type high concentration impurities are introduced by an ion implantation with the use of separate masks on the polycrystalline silicon layer of NMOS transistors and PMOS transistors with a low breakdown voltage and a high breakdown voltage. Then, a second gate electrode is formed by anisotropic etching. With the steps as described above, a first gate electrode inside the trench and the second gate electrode to be used in the lateral MOS transistor are laminated, to thereby reduce fluctuations due to the etching.Type: GrantFiled: December 20, 2012Date of Patent: November 5, 2013Assignee: Seiko Instruments Inc.Inventor: Yukimasa Minami
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Patent number: 8324708Abstract: Provided is a semiconductor integrated circuit device including fuse elements for carrying out laser trimming processing, in which a space width between aluminum interconnects of the first layer to be connected to the adjacent fuse elements is set to less than twice of the thickness of the side wall of the metal interlayer insulating film of the first layer, thereby preventing exposure of the SOG layer having hygroscopic property. In addition, side spacers are provided to side surfaces of the aluminum interconnects of the first layer.Type: GrantFiled: September 22, 2010Date of Patent: December 4, 2012Assignee: Seiko Instruments Inc.Inventors: Yukimasa Minami, Masaru Akino
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Publication number: 20110073986Abstract: Provided is a semiconductor integrated circuit device including fuse elements for carrying out laser trimming processing, in which a space width between aluminum interconnects of the first layer to be connected to the adjacent fuse elements is set to less than twice of the thickness of the side wall of the metal interlayer insulating film of the first layer, thereby preventing exposure of the SOG layer having hygroscopic property. In addition, side spacers are provided to side surfaces of the aluminum interconnects of the first layer.Type: ApplicationFiled: September 22, 2010Publication date: March 31, 2011Inventors: Yukimasa Minami, Masaru Akino
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Patent number: 7652525Abstract: A current mirror circuit has a first MOS transistor to which an input current is supplied. The first MOS transistor has a gate formed of polysilicon. A second MOS transistor has a gate formed of polysilicon and connected directly to the gate of the first MOS transistor via a polysilicon layer for producing an output current whose magnitude is a magnitude of the input current multiplied by a current mirror ratio. A fuse has one terminal connected to a gate portion between the gate of the first MOS transistor and the gate of the second MOS transistor and another terminal that is grounded.Type: GrantFiled: February 22, 2008Date of Patent: January 26, 2010Assignee: Seiko Instruments Inc.Inventor: Yukimasa Minami
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Publication number: 20090160057Abstract: A semiconductor device is provided in which penetration of a metal into a high impurity-doped active region from a side wall portion of a contact hole is prevented by reducing an aspect ratio to improve coverage of a titanium nitride film for the side wall portion of the contact hole, and in which increase in current consumption is eliminated. In a semiconductor device including an interlayer insulating film formed on a silicon substrate, and a interconnection formed of a barrier metal film and an aluminum alloy film and connected to the silicon substrate through a contact hole of the interlayer insulating film, a low-concentration impurity layer is epitaxially grown on a bottom surface of the contact hole, whereby the aspect ratio is reduced to improve coverage of the titanium nitride film for the side wall portion of the contact hole, and penetration of the metal into the high impurity-doped active region from the side wall portion of the contact hole is prevented.Type: ApplicationFiled: December 4, 2008Publication date: June 25, 2009Inventor: Yukimasa Minami
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Publication number: 20080224737Abstract: Provided is a semiconductor device capable of evenly distributing an effect of charge on each gate of adjacent MOS transistors, which form a current mirror circuit, during a production process of the semiconductor device, by directly connecting the gates of the adjacent MOS transistors, which form the current mirror circuit, to each other with polysilicon and by further connecting a fuse, which is connected to a substrate, to a gate portion that is connected with the polysilicon, and capable of reducing the effect by dissipating the charge to the substrate. The fuse is cut off during a trimming process.Type: ApplicationFiled: February 22, 2008Publication date: September 18, 2008Inventor: Yukimasa Minami
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Patent number: 7405612Abstract: A Provided is an electronic device in which: alternating current power from an RF coil which receives an electromagnetic wave and converts the electromagnetic wave into power is rectified by a diode and a first capacitor; the power is stepped up by a charge pump type step-up circuit; the power stepped up by the step-up circuit is stored in a second capacitor by a charging and discharging circuit; and the stored power is supplied from the charging and discharging circuit to an RF transmission circuit.Type: GrantFiled: August 3, 2006Date of Patent: July 29, 2008Assignee: Seiko Instruments Inc.Inventors: Yukimasa Minami, Yoshifumi Yoshida, Fumiyasu Utsunomiya