Patents by Inventor Yukimune Watanabe

Yukimune Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7968396
    Abstract: A semiconductor device includes a semiconductor layer formed on an insulating layer; a gate electrode disposed on said semiconductor layer via a gate insulating film; a source/drain layer composed by including an alloy layer or a metal layer with a bottom surface in contact with the insulating layer, with joint surfaces to a channel region disposed along crystal orientation faces of said semiconductor layer; and impurity-doped layers formed in a self-aligned manner along interfaces of the alloy layer or the metal layer, and said semiconductor layer.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: June 28, 2011
    Assignees: Seiko Epson Corporation, Renesas Technology Corporation
    Inventors: Yukimune Watanabe, Shinji Migita, Nobuyuki Mise
  • Patent number: 7947560
    Abstract: A method for forming silicide includes the steps of: forming a nickel film on a silicon layer (or a silicon substrate); introducing nitrogen into at least one of the nickel film and the interface between the nickel film and the silicon layer (or the silicon substrate); and after the introduction of the nitrogen, applying heat treatment to the nickel film and the silicon layer (or the silicon substrate) under predetermined conditions to form a nickel disilicide layer.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: May 24, 2011
    Assignees: Seiko Epson Corporation, Renesas Technology Corporation
    Inventors: Yukimune Watanabe, Nobuyuki Mise, Shinji Migita
  • Patent number: 7713884
    Abstract: A semiconductor wafer is placed in a chamber of a film-deposition apparatus, and gas in the chamber is exhausted from a gas exhaust outlet. Then, with interrupting the exhaust, an inert gas is introduced into the chamber so that the chamber has a pressure of 133 Pa or higher and lower than 101325 Pa, and then a mixed gas of an inert gas and a source gas for depositing a metal oxide film is introduced into the chamber. Then, after exhausting the gas in the chamber, an oxidation gas is introduced into the chamber to react with the molecules of the source gas absorbed on the semiconductor wafer to form a metal oxide film on the semiconductor wafer. By repeating these steps, a metal oxide film having a desired film thickness is deposited on the semiconductor wafer with a film-thickness distribution by an ALD method.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: May 11, 2010
    Assignees: Renesas Technology Corp., Seiko Epson Corporation
    Inventors: Hiromi Ito, Yuuichi Kamimuta, Yukimune Watanabe, Shinji Migita
  • Publication number: 20100072551
    Abstract: A semiconductor device includes a semiconductor layer formed on an insulating layer; a gate electrode disposed on said semiconductor layer via a gate insulating film; a source/drain layer composed by including an alloy layer or a metal layer with a bottom surface in contact with the insulating layer, with joint surfaces to a channel region disposed along crystal orientation faces of said semiconductor layer; and impurity-doped layers formed in a self-aligned manner along interfaces of the alloy layer or the metal layer, and said semiconductor layer.
    Type: Application
    Filed: November 25, 2009
    Publication date: March 25, 2010
    Applicants: SEIKO EPSON CORPORATION, RENESAS TECHNOLOGY CORPORATION
    Inventors: Yukimune Watanabe, Shinji Migita, Nobuyuki Mise
  • Patent number: 7645655
    Abstract: A semiconductor device includes a semiconductor layer formed on an insulating layer; a gate electrode disposed on said semiconductor layer via a gate insulating film; a source/drain layer composed by including an alloy layer or a metal layer with a bottom surface in contact with the insulating layer, with joint surfaces to a channel region disposed along crystal orientation faces of said semiconductor layer; and impurity-doped layers formed in a self-aligned manner along interfaces of the alloy layer or the metal layer, and said semiconductor layer.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: January 12, 2010
    Assignees: Seiko Epson Corporation, Renesas Technology Corporation
    Inventors: Yukimune Watanabe, Shinji Migita, Nobuyuki Mise
  • Publication number: 20080318439
    Abstract: A semiconductor wafer is placed in a chamber of a film-deposition apparatus, and gas in the chamber is exhausted from a gas exhaust outlet. Then, with interrupting the exhaust, an inert gas is introduced into the chamber so that the chamber has a pressure of 133 Pa or higher and lower than 101325 Pa, and then a mixed gas of an inert gas and a source gas for depositing a metal oxide film is introduced into the chamber. Then, after exhausting the gas in the chamber, an oxidation gas is introduced into the chamber to react with the molecules of the source gas absorbed on the semiconductor wafer to form a metal oxide film on the semiconductor wafer. By repeating these steps, a metal oxide film having a desired film thickness is deposited on the semiconductor wafer with a film-thickness distribution by an ALD method.
    Type: Application
    Filed: June 19, 2008
    Publication date: December 25, 2008
    Inventors: Hiromi Ito, Yuuichi Kamimuta, Yukimune Watanabe, Shinji Migita
  • Publication number: 20080303119
    Abstract: A method of manufacturing a semiconductor device includes forming a metal oxide on a semiconductor substrate, forming a gate electrode film on the metal oxide, and executing a thermal treatment on the semiconductor substrate provided with the metal oxide and the gate electrode film to crystallize the metal oxide.
    Type: Application
    Filed: May 1, 2008
    Publication date: December 11, 2008
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Yukimune WATANABE
  • Publication number: 20080067590
    Abstract: It is an object of the present invention to provide a technology which can form a sidewall without deteriorating device characteristics. A gate insulating film formed of a high dielectric constant film and a polysilicon film are formed on a semiconductor substrate. By patterning the polysilicon film, silicon gate electrodes are formed. Subsequently, a laminated film of an aluminum oxide film and a silicon nitride film is formed on the semiconductor substrate. Thereafter, the silicon nitride film is anisotropically dry-etched to leave silicon nitride films only on sidewalls of the silicon gate electrodes. At this time, the aluminum oxide film formed under the silicon nitride film functions as an etching stopper. Then, the exposed aluminum oxide film is wet-etched using diluted hydrofluoric acid.
    Type: Application
    Filed: May 11, 2007
    Publication date: March 20, 2008
    Inventors: Nobuyuki Mise, Kunihiko Iwamoto, Yukimune Watanabe, Shinji Migita
  • Publication number: 20070202692
    Abstract: A method for forming silicide includes the steps of: forming a nickel film on a silicon layer (or a silicon substrate); introducing nitrogen into at least one of the nickel film and the interface between the nickel film and the silicon layer (or the silicon substrate); and after the introduction of the nitrogen, applying heat treatment to the nickel film and the silicon layer (or the silicon substrate) under predetermined conditions to form a nickel disilicide layer.
    Type: Application
    Filed: February 21, 2007
    Publication date: August 30, 2007
    Applicants: SEIKO EPSON CORPORATION, RENESAS TECHNOLOGY CORPORATION
    Inventors: Yukimune Watanabe, Nobuyuki Mise, Shinji Migita
  • Publication number: 20060284220
    Abstract: A semiconductor device includes a semiconductor layer formed on an insulating layer; a gate electrode disposed on said semiconductor layer via a gate insulating film; a source/drain layer composed by including an alloy layer or a metal layer with a bottom surface in contact with the insulating layer, with joint surfaces to a channel region disposed along crystal orientation faces of said semiconductor layer; and impurity-doped layers formed in a self-aligned manner along interfaces of the alloy layer or the metal layer, and said semiconductor layer.
    Type: Application
    Filed: June 5, 2006
    Publication date: December 21, 2006
    Applicants: SEIKO EPSON CORPORATION, THE NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, RENESAS TECHNOLOGY CORPORATION
    Inventors: Yukimune Watanabe, Shinji Migita, Nobuyuki Mise
  • Publication number: 20060281273
    Abstract: A semiconductor device includes a gate electrode disposed on a semiconductor layer via a gate insulating film; a source layer formed in the semiconductor layer to be separated by a first offset length from one end of said gate electrode; a drain layer formed in the semiconductor layer to be separated by a second offset length from the other end of said gate electrode; a first side wall formed at a side wall of said gate electrode at a side of said source layer; and a second side wall formed at the side wall of said gate electrode at a side of said drain layer, wherein the first offset length is shorter than the second offset length, and a length of said first side wall is shorter than a length of said second side wall.
    Type: Application
    Filed: June 5, 2006
    Publication date: December 14, 2006
    Applicants: SEIKO EPSON CORPORATION, RENESAS TECHNOLOGY CORPORATION
    Inventors: Yukimune Watanabe, Shinji Migita, Nobuyuki Mise