Abstract: A timing recovery circuit includes a clock generation circuit which generates clock signals having different periods in different modes, i.e., a first and a second operation mode, phase interpolation circuits each of which outputs a sample timing signal having a phase adjusted to fall between the phases of two clock signals in the first operation mode, and outputs one of the two clock signals as a sample timing signal in the second operation mode, sampler circuits which latch a data signal using the sample timing signals, and a phase control circuit which gives an instruction to select a clock signal or adjust the phase of a sample timing signal.

Abstract: A timing recovery circuit includes a clock generation circuit which generates clock signals having different periods in different modes, i.e., a first and a second operation mode, phase interpolation circuits each of which outputs a sample timing signal having a phase adjusted to fall between the phases of two clock signals in the first operation mode, and outputs one of the two clock signals as a sample timing signal in the second operation mode, sampler circuits which latch a data signal using the sample timing signals, and a phase control circuit which gives an instruction to select a clock signal or adjust the phase of a sample timing signal.

Abstract: A comparison period determiner (110) detects whether or not a change occurs in received data during a comparison period including a timing at which a rising edge of a reference clock occurs. A phase determiner (120) determines whether a rising edge of the received data is located before or after the reference clock and determines whether a falling edge of the received data is located before or after the reference clock, and outputs a first determination signal and a second determination signal indicating results of the respective determinations. A synchronous data generator (130) outputs a signal having a level depending on a result of the detection by the comparison period determiner (110) and an output of the phase determiner (120), as synchronous data, in synchronization with a synchronization clock.

Abstract: A comparison period detecting unit (11) defines, as a comparison period, a period between a rising edge of a first clock signal and a rising edge of a second clock signal, and detects the presence or absence of transition of a data signal during the comparison period. A phase relationship detecting unit (12) detects a phase relationship between the data signal and a reference clock signal, and outputs a result of detection of the phase relationship when the comparison period detecting unit (11) detects transition of the data signal during the comparison period.

Abstract: An interface circuit including an LSI (10) in a host device (1), and an LSI (20) in a sub device (2), respectively. The LSI (10) generates a first transmission clock signal (TC1) and a first reception clock signal (RC1) separately in accordance with a first reference clock signal (RFC1). The LSI (10) also generates a second reference clock signal (RFC2) for a sub device (2). The reference clock signal (RFC2) is converted into a differential clock signal, and then transmitted to the sub device (2). An LSI (20) of the sub device (2) generates a second transmission clock signal (TC2) and a second reception clock signal (RC2) separately in accordance with a third reference clock signal (RFC3) converted from the differential clock signal.

Abstract: A phase comparison process in a timing recovery process for high-speed data communication defines a data window and compares the phase of a clock in the window with the phase of an edge of data so as to realize a parallel process, wherein the phase comparison and the process of determining whether a data edge lies within the window are performed in parallel to each other, and the phase comparison result is output only if the data edge lies within the window. With this configuration, it is possible to perform an accurate phase comparison process with no errors without requiring high-precision delay circuits.

Abstract: A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).

Abstract: A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).

Abstract: An ACS circuit includes: a basic DPM retaining section (11) for retaining basic DPMs (differential path metrics); a basic DPM calculating section (12) for calculating the basic DPMs; a reference DPM calculating section (13) for calculating reference DPMs, which are DPMs other than the basic DPMs; a basic DBM calculating section (14) for calculating basic DBMs (differential branch metrics), which are DBMs necessary for calculating the basic DPMs; and a path selecting section (15) for selecting the most likely paths for Viterbi decoding in accordance with the basic DPMs, the reference DPMs and the basic DBMs. The basic DPM calculating section (12) calculates new basic DPMs in accordance with the basic DPMs, the reference DPMs, the basic DBMs, and the results of the most likely path selection by the path selecting section (15).

Abstract: A comparison period determiner (110) detects whether or not a change occurs in received data during a comparison period including a timing at which a rising edge of a reference clock occurs. A phase determiner (120) determines whether a rising edge of the received data is located before or after the reference clock and determines whether a falling edge of the received data is located before or after the reference clock, and outputs a first determination signal and a second determination signal indicating results of the respective determinations. A synchronous data generator (130) outputs a signal having a level depending on a result of the detection by the comparison period determiner (110) and an output of the phase determiner (120), as synchronous data, in synchronization with a synchronization clock.

Abstract: A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).

Abstract: A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).

Abstract: A path memory circuit for use in a Viterbi decoding process performed based on state transitions through a number n (n is a positive integer) of states. The path memory circuit includes a memory area A formed by the storage circuits of the first to ith (i is an integer from 0 to M) stages; a memory area B formed by the selective storage circuits that select and hold a decoding result for any state k (k is integer from 1 to n) of the storage circuits from the i+1th stage to the Mth stage; and a memory area C formed by the selective storage circuits other than the memory area A and the memory area B.

Abstract: A comparison period detecting unit (11) defines, as a comparison period, a period between a rising edge of a first clock signal and a rising edge of a second clock signal, and detects the presence or absence of transition of a data signal during the comparison period. A phase relationship detecting unit (12) detects a phase relationship between the data signal and a reference clock signal, and outputs a result of detection of the phase relationship when the comparison period detecting unit (11) detects transition of the data signal during the comparison period.

Abstract: A phase comparison process in a timing recovery process for high-speed data communication defines a data window and compares the phase of a clock in the window with the phase of an edge of data so as to realize a parallel process, wherein the phase comparison and the process of determining whether a data edge lies within the window are performed in parallel to each other, and the phase comparison result is output only if the data edge lies within the window. With this configuration, it is possible to perform an accurate phase comparison process with no errors without requiring high-precision delay circuits.

Abstract: A PLL comprises a current-controlled oscillator (18) for generating an output clock signal based on a current signal generated based on a phase difference between a reference clock signal and a feedback clock signal, a current source (28), and an initialization switch (26) for performing an open/close operation based on the initialization signal, the initialization switch being inserted in series to an input terminal of the current-controlled oscillator (18) and the current source (28).

Abstract: When a signal cable is connected between communication nodes 0, 1 which comply with a communication protocol that inhibits loop connection, communication node 0 detecting connection of the signal cable transmits a loop test signal LT having information of a port where connection was detected (e.g., information of a transfer rate between ports). In response to the loop test signal LT, a communication node 2 adds information of its own port that received the loop test signal LT, that is, P(2, 1), to the received loop test signal LT, and repeats the loop test signal LT. Similarly, communication node 1 adds information of its own port that received the loop test signal LT, that is, P(1, 0), to the loop test signal LT. Communication node 0 specifies a suitable disconnection point of a loop (e.g., a port having a low transfer rate between ports) based on the port information thus accumulated.

Abstract: An integrated circuit device includes at least one functional module which outputs save data in synchronism with a saving clock signal, a power supply control unit which selects one of the functional modules, and controls stop and resumption of power supply to the selected functional module, a save data storage unit which stores save data output from a functional module selected by the power supply control unit, and an error checking and correction unit which performs error checking and correction for the save data stored in the save data storage unit when the save data is to be restored to the functional module in synchronism with a restoration clock signal.

Abstract: An ACS circuit includes: a basic DPM retaining section (11) for retaining basic DPMs (differential path metrics); a basic DPM calculating section (12) for calculating the basic DPMs; a reference DPM calculating section (13) for calculating reference DPMs, which are DPMs other than the basic DPMs; a basic DBM calculating section (14) for calculating basic DBMs (differential branch metrics), which are DBMs necessary for calculating the basic DPMs; and a path selecting section (15) for selecting the most likely paths for Viterbi decoding in accordance with the basic DPMs, the reference DPMs and the basic DBMs. The basic DPM calculating section (12) calculates new basic DPMs in accordance with the basic DPMs, the reference DPMs, the basic DBMs, and the results of the most likely path selection by the path selecting section (15).

Abstract: When a storage circuit (13) of a certain stage and those of the following stages are caused to stop, a storage element circuit (11) of a memory area B (2) that stores survivor paths of a particular state is caused to serve as a repeater, and the other storage element circuits (11), which belong to a memory area C (3) are caused to stop, whereby a decoding result can be outputted without using additional bus wires and selectors.