Abstract: To provide a simple highly-pure Xe retrieval method and device with high retrieval efficiency by functionally removing such elements as water, CO2 and FCs from waste gases from semiconductor production processes, such as the plasma etching, that contain low-concentration Xe. For samples containing xenon and fluorocarbon, this invention is characterized by having at least first adsorption means (A1) filled with synthetic zeolite with pore size of 4A or smaller and aluminum oxide, arranged serially, gas separation means (A2) composed of silicone or polyethylene hollow fiber gas separation membrane modules 4, second adsorption means (A3) filled with either activated carbon, synthetic zeolite with pore size of 5A or larger, molecular sieving carbon with pore size of 5A or larger, or a combination of these, and reaction means (A4) filled with calcium compounds as reactant.

Abstract: A processing apparatus is disclosed which is capable of switching supplies of a raw material gas and a reducing gas alternately, while continuously forming a plasma of the reducing gas. An excitation device (12) excites a reducing gas supplied thereinto, and the excited reducing gas is supplied into a process chamber (2). A switching mechanism (20) is arranged between the excitation device (12) and the process chamber (2), and a bypass line (22) is connected to the switching mechanism (20). The switching mechanism (20) switches the flow of the excited reducing gas from the excitation device (12) between the process chamber (2) and the bypass line (22).

Abstract: To provide a simple highly-pure Xe retrieval method and device with high retrieval efficiency by functionally removing such elements as water, CO2 and FCs from waste gases from semiconductor production processes, such as the plasma etching, that contain low-concentration Xe. For samples containing xenon and fluorocarbon, this invention is characterized by having at least first adsorption means (A1) filled with synthetic zeolite with pore size of 4A or smaller and aluminum oxide, arranged serially, gas separation means (A2) composed of silicone or polyethylene hollow fiber gas separation membrane modules 4, second adsorption means (A3) filled with either activated carbon, synthetic zeolite with pore size of 5A or larger, molecular sieving carbon with pore size of 5A or larger, or a combination of these, and reaction means (A4) filled with calcium compounds as reactant.

Abstract: A film fabrication method for forming a film over a substrate in a processing chamber includes a first film formation process and a second film formation process. In the first film formation process, (a) a first step of supplying a first source gas containing a metal-organic compound and without containing a halogen element into the chamber and then removing the first source gas from the chamber, and (b) a second step of supplying a second source gas containing hydrogen or a hydrogen compound into the chamber and then removing the second source gas from the chamber, are repeated a predetermined number of times.

Abstract: A processing apparatus is disclosed which is capable of switching supplies of a raw material gas and a reducing gas alternately, while continuously forming a plasma of the reducing gas. An excitation device (12) excites a reducing gas supplied thereinto, and the excited reducing gas is supplied into a process chamber (2). A switching mechanism (20) is arranged between the excitation device (12) and the process chamber (2), and a bypass line (22) is connected to the switching mechanism (20). The switching mechanism (20) switches the flow of the excited reducing gas from the excitation device (12) between the process chamber (2) and the bypass line (22).

Abstract: Edge face sealing member(s) may be roughly c-shaped in cross-section, may be frame-like in shape and formed in more or less parallel fashion with respect to outer shape(s) of solar cell module body or bodies, may comprise upper sealing region(s) abutting front surface(s) of solar cell module body or bodies, may further comprise lower sealing region(s) abutting back surface(s) of solar cell module body or bodies, and may further comprise side sealing region(s) abutting edge face(s) of solar cell module body or bodies.

Abstract: An optical switch comprising an array of voltage-controlled interferometric switching elements. Different configurations and modes of operation are possible, but in each configuration the elements are arranged relative to the input and output fibers, such that a beam of light is incident or outgoing at an angle of 45 degrees to the surface of a corresponding element. This permits each element to be electronically controlled to either transmit or reflect light, such that the output beam exits the switch either parallel to or perpendicular to the input beam.

Abstract: A photovoltaic module including: a light-transmissive substrate; a first sealing polymer layer stacked on the substrate; a photovoltaic cell stacked on the first sealing polymer layer; a second sealing polymer layer stacked on the photovoltaic cell and a weatherproof film stacked on the second sealing polymer layer, wherein the weatherproof film includes a moisture-proof layer provided on the second sealing polymer layer and a gas-proof layer provided on the moisture-proof layer, the gas-proof layer being made of polyphenylene sulfide.

Abstract: A barrier layer (20, 62) for an integrated circuit structure is disclosed. The barrier layer (20, 62) is a refractory metal silicon compound, such as a refractor metal silicon nitride compound, formed in an amorphous state. The barrier layer (20, 62) has a relatively low composition ratio of silicon, and of nitrogen if present, to provide low resistivity in combination with the high diffusion barrier properties provided by the amorphous state of the film. A disclosed example of the barrier layer (20, 62) is a compound of tantalum, silicon, and nitrogen, formed by controlled co-sputtering of tantalum and silicon in a gas atmosphere including nitrogen and argon. The barrier layer (20) may be used to underlie copper metallization (22), or the barrier layer (62) may be part or all of a lower plate in a ferroelectric memory capacitor (70).

Abstract: Edge face sealing member(s) 1 may be roughly c-shaped in cross-section, may be frame-like in shape and formed in more or less parallel fashion with respect to outer shape(s) of solar cell module body or bodies, may comprise upper sealing region(s) 11 abutting front surface(s) of solar cell module(s), may further comprise lower sealing region(s) 12 abutting back surface(s) of solar cell module(s), and may further comprise side sealing region(s) 13 abutting edge face(s) of solar cell module(s). Furthermore, respectively formed on facing surfaces of upper sealing region(s) 11 and lower sealing region(s) 12 there may be projections 11b, 12b. Furthermore, polypropylenic and/or polystyrenic elastomer resin(s) may be used as material(s) making up edge face sealing member(s) 1, and magnesium silicate may be present as additive(s) for prevention of yellowing of sealing resin layer(s) at solar cell module body or bodies.

Abstract: A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state.

Abstract: A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state.

Abstract: A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state.

Abstract: A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state.

Abstract: A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state.

Abstract: A ferroelectric memory structure is described for the 1T1C arrangement in a ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state.

Abstract: An optical switch comprising an array of voltage-controlled interferometric switching elements. Different configurations and modes of operation are possible, but in each configuration the elements are arranged relative to the input and output fibers, such that a beam of light is incident or outgoing at an angle of 45 degrees to the surface of a corresponding element. This permits each element to be electronically controlled to either transmit or reflect light, such that the output beam exits the switch either parallel to or perpendicular to the input beam.

Abstract: A ferroelectric memory structure is described for the 1T1C arrangement in ferroelectric capacitor cell array for FeRAM memory device applications. The device structure provides an accurate reference voltage and a simple sensing scheme for the sense amplifier used for reading the state of a target memory cell of the FeRAM array. A reference circuit generates a reference voltage which is a function of a charge shared between a plurality of FeRAM dummy cells. Each dummy cell of the plurality of FeRAM dummy cells is selectively coupleable to a plurality of bitlines. A shorting transistor in the reference circuit couples two bitlines or two bitline-bars neighboring the selected target memory cell. One dummy cell is coupled to a select one of the two shorted bitlines or bitline-bars, and another dummy cell is coupled to a another of the two shorted bitlines or bitline-bars, wherein at least one dummy cell is biased to a “0” state, and at least one other dummy cell is biased to a “1” state.

Abstract: A photovoltaic module including: a light-transmissive substrate; a first sealing polymer layer stacked on the substrate; a photovoltaic cell stacked on the first sealing polymer layer; a second sealing polymer layer stacked on the photovoltaic cell and a weatherproof film stacked on the second sealing polymer layer, wherein the weatherproof film includes a moisture-proof layer provided on the second sealing polymer layer and a gas-proof layer provided on the moisture-proof layer, the gas-proof layer being made of polyphenylene sulfide.

Abstract: The purpose of this invention is to provide a method for manufacturing capacitors free of polarization fatigue even when the treatment is performed at a low temperature. Amorphous layer 32 made of lead zirconate titanate and containing excess lead is formed on lower electrode 13 made of iridium. The amorphous layer is crystallized by a heat treatment to form PZT film 14. Structural transition layer 33 containing excess Pb formed on the surface of PZT film 14 during the aforementioned crystallization is removed by means of dry etching. In this way, a PZT capacitor is obtained.