Abstract: An object is to provide a memory element having a novel structure where data can be held even after power supply is stopped. The memory element includes a latch circuit, a first selection circuit, a second selection circuit, a first nonvolatile memory circuit, and a second nonvolatile memory circuit. The first nonvolatile memory circuit and the second nonvolatile memory circuit each include a transistor and a capacitor. The transistor included in each of the first nonvolatile memory circuit and the second nonvolatile memory circuit is a transistor in which a channel is formed in an oxide semiconductor film. The off-state current of such a transistor is extremely small. The transistor is turned off after data is input to a node where the transistor and the capacitor are connected to each other, and data can be held for a long time even after supply of power supply voltage is stopped.

Abstract: To provide a signal processing circuit including a nonvolatile memory circuit with a novel structure, the signal processing circuit includes an arithmetic portion, a memory, and a control portion for controlling the arithmetic portion and the memory. The control portion includes a set of a volatile memory circuit and a first nonvolatile memory circuit for storing data held in the volatile memory circuit, the memory includes a plurality of second nonvolatile memory circuits, and the first nonvolatile memory circuit and the second nonvolatile memory circuit each include a transistor having a channel in an oxide semiconductor layer and a capacitor in which one of a pair of electrodes is electrically connected to a node which is set in a floating state when the transistor is turned off.

Abstract: A data transfer controller for controlling DMA data transfer between a memory area and a peripheral unit. The data transfer controller has a first register which stores address information relative to a predetermined address of the memory area. A DMA control unit uses the first register and a second register to perform the DMA data transfer between the memory area and the peripheral unit. The data transfer controller also has a third register for storing data used for accessing the memory area of the DMA transfer. An updater is used to update the contents of the third register whenever a memory access uses the third register and is different from a memory access associated with data transfer between the memory area and the peripheral unit. Finally, a counter changes the contents of the third register in one direction whenever the data transfer between the memory area and the peripheral unit is performed.

Abstract: An information processor has at least one interface unit by which the processor is coupled to a peripheral equipment. The interface unit can selectively generate either a first mode signal or a second mode signal when the processor performs and interruption operation according to request from the peripheral equipment. When the processor performs the interruption operation in response to the first mode signal, a stack operation for saving information necessary to restart a program execution which is stopped by the interruption to a stack memory is performed before start of the interruption operation. While the processor can perform the interruption operation in response to the second mode signal without the stack operation, whereby an improved processor with less overhead can be provided.

Abstract: An information processor has at least one interface unit by which the processor is coupled to a peripheral equipment. The interface unit can selectively generate either a first mode signal or a second mode signal when the processor performs an interruption operation according to request from the peripheral equipment. When the processor performs the interruption operation in response to the first mode signal, a stack operation for saving information necessary to restart a program execution which is stopped by the interruption to a stack memory is performed before start of the interruption operation. While the processor can perform the interruption operation in response to the second mode signal without the stack operation, whereby an improved processor with less overhead can be provided.

Abstract: A CPU includes a program counter, an execution unit, and a program status word register. A pulse producing unit connected to the CPU includes a plurality of output terminals, a port selection register for designating at least one of the output terminals, and a system for generating a pulse start timing signal, a system responsive to the pulse start timing signal for bringing the designated output terminal into one of two bistable logic states. A counter counts a clock pulse signal and brings the selected output terminal into the other of the bistable logic states when the counter indicates a predetermined elapsed time. Another system responsive to the pulse start timing signal sends a signal to the CPU requesting a macro service operation.

Abstract: An information processor has at least one interface unit by which the processor is coupled to peripheral equipment. The interface unit can selectively generate either a first mode signal or a second mode signal when the processor performs an interruption operation according to request from the peripheral equipment. When the processor performs the interruption operation in response to the first mode signal, a stack operation for saving information necessary to restart execution of a program which is stopped by the interruption in a stack memory is performed before the start of the interruption operation. The processor can perform the interruption operation in response to the second mode signal without the stack operation, providing an improved processor with less overhead. The two interruption mode technique is described in a number of applications, including D/A conversion, serial data transmission and reception, and operation of computer peripheral devices.

Abstract: A serial clock generating circuit for generating a serial clock in phase with a clock included in a received serial data on the basis of an input clock having a frequency N times of a serial data transfer rate of the received serial data, comprises an edge detector for detecting a level transition of the received serial data so as to generate a level transition detection signal, and a counter for counting the input clock. A first comparison register is provided for comparing a count value of the counter with a first programmable predetermined value at each one counting operation of the counter, so as to generate a first coincidence signal when the count value of the counter is coincident with the first programmable predetermined value.

Abstract: Herein disclosed is a serial data transfer system which has first and second serial data processors connected via a single data line and a single clock line for transferring serial data therebetween. Each of the first and second serial data processors includes: reception confirmation signal output means for outputting a reception confirmation signal to the data line; and reception confirmation signal detection means for detecting the reception confirmation signal on the data line. The confirmation of the data transfer is executed in synchronism with serial clock pulses outputted to the clock line. Alternatively, the first or second serial data processor includes: an output circuit for outputting a reception confirmation signal to the data line; a circuit for generating a first signal indicating the end of reception of the serial data; a circuit for generating a second signal indicating the end of processing of the data received; and a circuit for controlling the output of said reception confirmation signal.

Abstract: A serial data processor is coupled to a single data line and a single clock line for serial data transfer in synchronism with a clock signal. The data processor comprises a shift register coupled to the serial data line and operated to serially output the data in synchronism with a clock on the clock line, and an output buffer connected to receive the data serially outputted from the shift register and coupled to sequentially output the received data to the data line. This output buffer includes a push-pull driver having an output connected to the data line and an input driven by the data serially outputted from the shift register. A clock counter is coupled to receive the clock on the clock line so as to maintain the push-pull driver in an operable condition until the count value reaches a predetermined value and to bring the output of the push-pull driver into a floating condition after the count value reached a predetermined value.

Abstract: An information processing apparatus with a dual processor system contains a general purpose processor for processing a required program and a special purpose processor for processing a specific operation in the required program. The special purpose processor is designed according to a data flow architecture and executes a task according to a token prepared by the general purpose processor, the token having a sequence control information and a data to be processed.

Abstract: A data processor comprises an interrupt processing request controller receiving processing requests from peripheral devices for generating an interrupt request. An execution unit has a first mode of executing the interrupt processing in accordance with a user's program and a second mode of executing the interrupt processing in accordance with a microprogram while maintaining an internal condition concerning execution of a program. The controller operates to selectively inhibit the execution of the interrupt processing in the first mode, but to basically allow the execution of the interrupt processing in the second mode.

Abstract: A microcomputer system comprises a microprocessor and a memory chip which has on a single semiconductor substrate a pointer for indicating an address of an instruction code fetch destination, an incrementer for incrementing the pointer and a memory for storing programs and data. The microprocessor controls the update timing of the pointer in the memory chip, so that the instruction codes can be continuously read from the memory of the memory chip without outputting the addresses of the instruction code fetch destination from the microprocessor.

Abstract: An information processing apparatus with a dual processor system contains a general purpose processor for processing a required program and a special purpose processor for processing a specific operation in the required program. The special purpose processor is designed according to a data flow architecture and executes a task according to a token prepared by the general purpose processor, the token having sequence control information and data to be processed. The architecture employed enables placement of both the general purpose processor and the single purpose processor on a single semiconductor chip, and also enables asynchronous, parallel operation of the two processors.

Abstract: A serial data communication system is disclosed. This system includes a plurality of stations which are interconnected by a single clock wire and a single data wire. A master station in the stations includes a transistor push-pull circuit for driving the clock wire to output a clock signal on the clock wire. The clock signal thus has sharp leading and falling edges. The data wire is coupled to wire logic means. A transmitting station transmits each bit of a data signal on the data wire in synchronism with one of leading and falling edges of the associated clock pulse of the clock signal, and a receiving station receives each bit of the data signal in synchronism with the other of leading and falling edges of the associated clock pulse.

Abstract: A microprocessor includes a central processing unit which executes a program according to at least one control signal generated by an instruction decoder. The instruction decoder is designed such that a first type instruction compatible for the central processing unit can be decoded. A second type instruction not compatible for the central processing unit is applied as an address to a conversion memory in which a first type instruction corresponding in function to the second type instruction has been stored. The first type instruction in the conversion memory is then applied to the instruction decoder instead of the second type instruction. Thus, the second type instruction can be executed by the central processing unit which is not otherwise compatible with the second type instruction.

Abstract: An interruption control apparatus includes registers storing priority data and a circuit producing scanning data in a priority order. The priority data is compared with the scanning data by a scanning operation. If the priority data is equal to the scanning data, a coincidence signal is generated. An interruption request signal from an interruption source is transferred to an interruption processing unit only when the coincidence signal is being generated. Thus, a priority control for a plurality of interruption requests can be performed by using a simple hardware circuit without complex software processing.

Abstract: A date data processor verifies whether an inputted date data exists or not. Inputted date data is stored in an input register which is composed of three sections according to month, day and year. A first calculating unit calculates the days difference between the inputted date data and a reference date, and the results are temporarily stored. A second calculating unit then performs an inverse calculating to arrive at a date based on the previously calculated days difference. The resulting date is compared with the inputted date to complete the verification.

Abstract: A clear signal generating circuit for initializing a logic circuit upon the application of power to the logic circuit. The generator circuit comprises a level detection circuit for generating a detection signal when the power supply voltage reaches or exceeds a predetermined value, a counter circuit which commences to count in response to the detection signal and which generates a trigger pulse upon reaching a predetermined count and a status storage circuit which is placed in a first state in response to the occurrence of the detection signal and placed in a second state in response to the trigger pulse. The output of the status storage circuit is utilized as the generator circuit output.

Abstract: A circuit for removing noise from an incoming input signal and for producing a noise free output signal in synchronism with a predetermined synchronization scheme. The memory signal is shifted through a plurality of series connected memory stages in sequence with first and second clock pulse sequences. The output signals of predetermined memory stages are compared and a noise free output signal is produced in response to stage output signals being simultaneously present at the output terminal of predetermined memory stages. The circuit does not utilize capacitors and resistors and is suitable for fabrication as an integrated circuit.