Patents by Inventor Yukio Maki
Yukio Maki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11476258Abstract: A semiconductor device includes a semiconductor substrate having a main surface, a gate electrode formed on the main surface of the semiconductor substrate, a side-wall oxide film formed on a side wall of the gate electrode, a first insulating layer formed on the gate electrode and containing silicon nitride, and a second insulating layer formed between the gate electrode and the first insulating layer and containing silicon oxide.Type: GrantFiled: April 30, 2019Date of Patent: October 18, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Yukio Maki
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Publication number: 20190259767Abstract: A semiconductor device includes a semiconductor substrate having a main surface, a gate electrode formed on the main surface of the semiconductor substrate, a side-wall oxide film formed on a side wall of the gate electrode, a first insulating layer formed on the gate electrode and containing silicon nitride, and a second insulating layer formed between the gate electrode and the first insulating layer and containing silicon oxide.Type: ApplicationFiled: April 30, 2019Publication date: August 22, 2019Inventor: Yukio MAKI
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Patent number: 9905512Abstract: An object of the invention is to provide a semiconductor device having less cracking or peeling and a method of manufacturing the same. A fuse portion of a semiconductor device has bit lines electrically coupled to a SRAM memory cell. The bit lines are covered by an interlayer insulating film. As the interlayer insulating film, a boron-doped BPTEOS film is formed. The bit lines have thereabove a fuse. The fuse and the bit lines are electrically coupled to each other via contact plugs. The interlayer insulating film that covers the bit lines therewith is separated from the contact plugs.Type: GrantFiled: February 5, 2016Date of Patent: February 27, 2018Assignee: Renesas Electronics CorporationInventors: Toshifumi Iwasaki, Yukio Maki
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Publication number: 20180040365Abstract: A semiconductor device which suppresses soft errors and functions as a non-volatile memory and a method for manufacturing the same. In the semiconductor device, a first non-volatile memory element and a second non-volatile memory element are electrically coupled to a first memory node and a second memory node through a first MOS transistor and a second MOS transistor respectively. A first capacitor and a second capacitor each have a storage node electrically coupled to the first memory node and the second memory node respectively and each have a cell plate to form a capacitance between the storage node and the cell plate.Type: ApplicationFiled: June 23, 2017Publication date: February 8, 2018Applicant: Renesas Electronics CorporationInventors: Yukio MAKI, Yoshiyuki ISHIGAKI, Toshiaki TAI, Hideaki YAMAKOSHI, Toshihiko HIROSE, Takuya ISHIDA
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Patent number: 9472495Abstract: Possible to form an opening having a sufficient opening diameter in a region sandwiched between a pair of bit lines and thereby provide a semiconductor device in which a high-quality contact using the opening is formed. The semiconductor device includes a first conductive layer, a first interlayer insulating film, a bit line, a first insulating film, a second interlayer insulating film, and a second conductive layer. The first insulating film that covers a side surface of the bit line has a portion perpendicular to a main surface of a semiconductor substrate in a region lower than a position lower than an uppermost portion of the first insulating film by a thickness, in a direction along the main surface of the semiconductor substrate, of the first insulating film that covers the side surface of the bit line at a lowermost portion of the bit line.Type: GrantFiled: January 15, 2014Date of Patent: October 18, 2016Assignee: Renesas Electronics CorporationInventor: Yukio Maki
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Publication number: 20160276270Abstract: An object of the invention is to provide a semiconductor device having less cracking or peeling and a method of manufacturing the same. A fuse portion of a semiconductor device has bit lines electrically coupled to a SRAM memory cell. The bit lines are covered by an interlayer insulating film. As the interlayer insulating film, a boron-doped BPTEOS film is formed. The bit lines have thereabove a fuse. The fuse and the bit lines are electrically coupled to each other via contact plugs. The interlayer insulating film that covers the bit lines therewith is separated from the contact plugs.Type: ApplicationFiled: February 5, 2016Publication date: September 22, 2016Applicant: Renesas Electronics CorporationInventors: Toshifumi IWASAKI, Yukio MAKI
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Patent number: 9368504Abstract: Variations in the contact area between contact plugs are suppressed to suppress fluctuations in contact resistance. In three third interlayer insulating films, a contact hole is self-alignedly formed to extend through the portions thereof interposed between two wiring portions and the portions thereof interposed between two gate wiring portions and reach a first polysilicon plug. In the contact hole, a second polysilicon plug is formed to come in contact with the first polysilicon plug.Type: GrantFiled: August 14, 2014Date of Patent: June 14, 2016Assignee: Renesas Electronics CorporationInventors: Kenji Adachi, Yukio Maki
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Publication number: 20150187645Abstract: A semiconductor device is provided, in which it becomes easy to reliably couple a plug conductive layer and a wiring layer located over the plug conductive layer to each other and falling of the wiring can be suppressed. The plug conductive layer contacts a source/drain region formed over a major surface of the semiconductor substrate. A contact conductive layer is formed so as to contact both the upper surface and the side surface of the plug conductive layer. Wiring layers are formed over the contact conductive layer so as to be electrically coupled to the contact conductive layer.Type: ApplicationFiled: March 10, 2015Publication date: July 2, 2015Inventor: Yukio Maki
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Patent number: 8987917Abstract: A semiconductor device is provided, in which it becomes easy to reliably couple a plug conductive layer and a wiring layer located over the plug conductive layer to each other and falling of the wiring can be suppressed. The plug conductive layer contacts a source/drain region formed over a major surface of the semiconductor substrate. A contact conductive layer is formed so as to contact both the upper surface and the side surface of the plug conductive layer. Wiring layers are formed over the contact conductive layer so as to be electrically coupled to the contact conductive layer.Type: GrantFiled: February 20, 2013Date of Patent: March 24, 2015Assignee: Renesas Electronics CorporationInventor: Yukio Maki
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Publication number: 20150076612Abstract: The semiconductor device includes a bit line, a word line intersecting the bit line, a plurality of first contact patterns, and a plurality of second contact patterns. The word line extends so as to intersect the bit line in plan view. Each of the first contact patterns is elongated in the direction in which the bit line extends in plan view. Each of the second contact patterns is elongated in directions inclined with respect to the respective directions in which the bit line and the word line extend in plan view. The first contact patterns and the second contact patterns are formed in the same layer over the main surface of a semiconductor substrate.Type: ApplicationFiled: August 18, 2014Publication date: March 19, 2015Inventor: Yukio MAKI
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Publication number: 20150076611Abstract: Provided are a semiconductor device in which the occurrence of a short circuit between a gate electrode and either of the source/drain regions of a transistor can be suppressed and a manufacturing method thereof. In the semiconductor device, a first insulating layer formed over the gate electrode and containing a silicon nitride has an upper surface having a depressed portion which is formed in a region over a second electrode layer of the gate electrode containing a silicide.Type: ApplicationFiled: August 18, 2014Publication date: March 19, 2015Inventor: Yukio MAKI
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Publication number: 20150076619Abstract: Variations in the contact area between contact plugs are suppressed to suppress fluctuations in contact resistance. In three third interlayer insulating films, a contact hole is self-alignedly formed to extend through the portions thereof interposed between two wiring portions and the portions thereof interposed between two gate wiring portions and reach a first polysilicon plug. In the contact hole, a second polysilicon plug is formed to come in contact with the first polysilicon plug.Type: ApplicationFiled: August 14, 2014Publication date: March 19, 2015Applicant: Renesas Electronics CorporationInventors: Kenji ADACHI, Yukio MAKI
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Publication number: 20140203441Abstract: Possible to form an opening having a sufficient opening diameter in a region sandwiched between a pair of bit lines and thereby provide a semiconductor device in which a high-quality contact using the opening is formed. The semiconductor device includes a first conductive layer, a first interlayer insulating film, a bit line, a first insulating film, a second interlayer insulating film, and a second conductive layer. The first insulating film that covers a side surface of the bit line has a portion perpendicular to a main surface of a semiconductor substrate in a region lower than a position lower than an uppermost portion of the first insulating film by a thickness, in a direction along the main surface of the semiconductor substrate, of the first insulating film that covers the side surface of the bit line at a lowermost portion of the bit line.Type: ApplicationFiled: January 15, 2014Publication date: July 24, 2014Applicant: Renesas Electronics CorporationInventor: Yukio MAKI
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Patent number: 8487312Abstract: To provide a semiconductor device with a TFT, capable of reducing the electric resistance of a power supply wiring without increasing the off-current. The semiconductor device includes an insulating film with a surface; a semiconductor layer which is formed over the surface of the insulating film and which includes a channel region and a pair of source/drain regions and sandwiching the channel region; and a power supply wiring for supplying power to the source region. A concave portion is formed in the surface of the insulating film. The power supply wiring includes a layer formed from the same layer as the semiconductor layer, and has a first portion formed over the surface of the insulating film and a second portion formed in the concave portion. The bottom of the second portion is covered with an insulator.Type: GrantFiled: May 16, 2012Date of Patent: July 16, 2013Assignee: Renesas Electronics CorporationInventor: Yukio Maki
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Publication number: 20120306029Abstract: To provide a semiconductor device with a TFT, capable of reducing the electric resistance of a power supply wiring without increasing the off-current. The semiconductor device includes an insulating film with a surface; a semiconductor layer which is formed over the surface of the insulating film and which includes a channel region and a pair of source/drain regions and sandwiching the channel region; and a power supply wiring for supplying power to the source region. A concave portion is formed in the surface of the insulating film. The power supply wiring includes a layer formed from the same layer as the semiconductor layer, and has a first portion formed over the surface of the insulating film and a second portion formed in the concave portion. The bottom of the second portion is covered with an insulator.Type: ApplicationFiled: May 16, 2012Publication date: December 6, 2012Inventor: Yukio MAKI
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Patent number: 7786534Abstract: A plurality of conductive layers and a plurality of wiring layers connecting a supporting substrate having SOI structure and uppermost wire are formed along a peripheral part of a semiconductor chip together with the uppermost wire, to thereby surround a transistor forming region in which a transistor is to be formed.Type: GrantFiled: March 6, 2009Date of Patent: August 31, 2010Assignee: Renesas Technology Corp.Inventors: Yukio Maki, Takashi Ipposhi, Toshiaki Iwamatsu
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Publication number: 20090194877Abstract: A plurality of conductive layers and a plurality of wiring layers connecting a supporting substrate having SOI structure and uppermost wire are formed along a peripheral part of a semiconductor chip together with the uppermost wire, to thereby surround a transistor forming region in which a transistor is to be formed.Type: ApplicationFiled: March 6, 2009Publication date: August 6, 2009Applicant: Renesas Technology Corp.Inventors: Yukio Maki, Takashi Ipposhi, Toshiaki Iwamatsu
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Patent number: 7535062Abstract: A plurality of conductive layers and a plurality of wiring layers connecting a supporting substrate having SOI structure and uppermost wire are formed along a peripheral part of a semiconductor chip together with the uppermost wire, to thereby surround a transistor forming region in which a transistor is to be formed.Type: GrantFiled: January 4, 2007Date of Patent: May 19, 2009Assignee: Renesas Technology Corp.Inventors: Yukio Maki, Takashi Ipposhi, Toshiaki Iwamatsu
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Publication number: 20080179676Abstract: While reducing the formation area of a SRAM cell, the variation in electrical characteristics of respective transistors is suppressed. In a SRAM cell formed in a SOI board, the electrical coupling between the drain region of a driver transistor (which is also a source/drain region of an access transistor), and the drain region of a load transistor, and the electrical coupling between the drain region of another driver transistor (which is also a source/drain region of another access transistor) and the drain region of another load transistor are established by wiring structures formed by using a SOI layer under an isolation oxide film which is partial trench isolation, respectively.Type: ApplicationFiled: January 9, 2008Publication date: July 31, 2008Inventors: Yuichi HIRANO, Takashi Ipposhi, Toshiaki Iwamatsu, Yukio Maki, Mikio Tsujiuchi
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Publication number: 20070158691Abstract: A plurality of conductive layers and a plurality of wiring layers connecting a supporting substrate having SOI structure and uppermost wire are formed along a peripheral part of a semiconductor chip together with the uppermost wire, to thereby surround a transistor forming region in which a transistor is to be formed.Type: ApplicationFiled: January 4, 2007Publication date: July 12, 2007Applicant: Renesas Technology Corp.Inventors: Yukio Maki, Takashi Ipposhi, Toshiaki Iwamatsu