Abstract: A semiconductor device according to the present invention includes: a semiconductor substrate including an active region and an isolation region; a gate electrode formed on the active region with an oxide film interposed therebetween; and a set of impurity regions formed on both sides of the gate electrode. A surface of the active region is entirely rounded so as to be inclined downward toward the isolation region. This rounded shape can be formed by forming an isolation oxide film such that a bird's beak portion is connected on the active region.

Abstract: A semiconductor memory device having as its main storage portion a capacitor storing charges as binary information and an access transistor controlling input/output of the charges to/from the capacitor, and eliminating the need for refresh, is obtained. The semiconductor memory device includes a capacitor with a storage node located above a semiconductor substrate and holding the charges corresponding to a logical level of stored binary information, an access transistor located on the semiconductor substrate surface and controlling input/output of the charges accumulated in the capacitor, and a latch circuit located on the semiconductor substrate and maintaining a potential of the capacitor storage node. At least one of circuit elements constituting the latch circuit is located above the access transistor.

Abstract: An SRAM comprises a memory cell including first and second access nMOS transistors, first and second driver nMOS transistors and first and second load pMOS transistors, polysilicon wires forming gates of the first and second access nMOS transistors and polysilicon wires extending in the same direction as the polysilicon wires for forming gates of the first and second driver nMOS transistors and gates of the first and second load pMOS transistors. The gate widths of the first and second access nMOS transistors and those of the first and second driver nMOS transistors are equalized with each other.

Abstract: A semiconductor device according to the present invention includes a silicon substrate having a main surface, a gate electrode provided on the main surface of the silicon substrate, a first sidewall insulating film provided to cover a side surface of the gate electrode and including two layers of an oxide sidewall film as an underlay and a nitride sidewall film, a second sidewall insulating film provided to cover a surface of the first sidewall insulating film, and a cobalt silicide layer arranged above source and drain regions and at a position farther than the second sidewall insulating film from the gate electrode. The second sidewall insulating film fills in a removed portion located at a lower end of the oxide sidewall film. This allows a semiconductor device formed by employing a salicide process to prevent increase of leak current caused by a metal silicide layer.

Abstract: An SRAM comprises a memory cell including first and second access nMOS transistors, first and second driver nMOS transistors and first and second load pMOS transistors, polysilicon wires forming gates of the first and second access nMOS transistors and polysilicon wires extending in the same direction as the polysilicon wires for forming gates of the first and second driver nMOS transistors and gates of the first and second load pMOS transistors. The gate widths of the first and second access nMOS transistors and those of the first and second driver nMOS transistors are equalized with each other.

Abstract: A semiconductor memory device having as its main storage portion a capacitor storing charges as binary information and an access transistor controlling input/output of the charges to/from the capacitor, and eliminating the need for refresh, is obtained. The semiconductor memory device includes a capacitor with a storage node located above a semiconductor substrate and holding the charges corresponding to a logical level of stored binary information, an access transistor located on the semiconductor substrate surface and controlling input/output of the charges accumulated in the capacitor, and a latch circuit located on the semiconductor substrate and maintaining a potential of the capacitor storage node. At least one of circuit elements constituting the latch circuit is located above the access transistor.

Abstract: A semiconductor device according to the present invention includes a silicon substrate having a main surface, a gate electrode provided on the main surface of the silicon substrate, a first sidewall insulating film provided to cover a side surface of the gate electrode and including two layers of an oxide sidewall film as an underlay and a nitride sidewall film, a second sidewall insulating film provided to cover a surface of the first sidewall insulating film, and a cobalt silicide layer arranged above source and drain regions and at a position farther than the second sidewall insulating film from the gate electrode. The second sidewall insulating film fills in a removed portion located at a lower end of the oxide sidewall film. This allows a semiconductor device formed by employing a salicide process to prevent increase of leak current caused by a metal silicide layer.

Abstract: A manufacturing process for a semiconductor device including a semiconductor memory region and a peripheral circuit region including bipolar transistors, in which a plurality of bipolar transistors with characteristics different from each other are effectively manufactured according to design requirements while minimizing the number of manufacturing steps. In manufacturing the semiconductor memory region and the bipolar transistors in the peripheral circuit region, a plurality of holes for forming the bipolar transistors are provided in the peripheral circuit region in correspondence to a plurality of steps for forming holes for interlayer insulating films in the semiconductor memory region, whereby the bipolar transistors with characteristics different from each other are formed in the holes of the peripheral region.

Abstract: Gate electrodes are formed on an element formation region of a silicon substrate. A sidewall insulation film having a width at least half the distance between the gate electrodes is formed on both side faces of respective gate electrodes. The distance L between the gate electrode and another gate electrode is greater than the distance between the gate electrodes. An n+ source region is formed in self-alignment at this region. Accordingly, a semiconductor device is obtained that has the symmetry of the characteristics of access transistors ensured and that has the contact resistance in the storage node contact reduced.

Abstract: Gate electrodes are formed on an element formation region of a silicon substrate. A sidewall insulation film having a width at least half the distance between the gate electrodes is formed on both side faces of respective gate electrodes. The distance L between the gate electrode and another gate electrode is greater than the distance between the gate electrodes. An n+ source region is formed in self-alignment at this region. Accordingly, a semiconductor device is obtained that has the symmetry of the characteristics of access transistors ensured and that has the contact resistance in the storage node contact reduced.

Abstract: A semiconductor device according to the present invention includes: a semiconductor substrate including an active region and an isolation region; a gate electrode formed on the active region with an oxide film interposed therebetween; and a set of impurity regions formed on both sides of the gate electrode. A surface of the active region is entirely rounded so as to be inclined downward toward the isolation region. This rounded shape can be formed by forming an isolation oxide film such that a bird's beak portion is connected on the active region.

Abstract: In a MOS semiconductor device including a normal MOS transistor and an output MOS transistor for an input/output buffer, the normal MOS transistor is formed in a normal well. In an output MOS transistor, the channel region of the second MOS transistor and an element isolation region are formed in the region of a higher impurity concentration. On the other hand, the source and drain regions are formed in a lower impurity concentration region. Thereby, the source/drain capacitance of the output MOS transistor may be reduced, and the input/output capacitance of the semiconductor device may be reduced.

Abstract: In a MOS semiconductor device including a normal MOS transistor and an output MOS transistor for an input/output buffer, the normal MOS transistor is formed in a normal well. In an output MOS transistor, the channel region of the second MOS transistor and an element isolation region are formed in the region of a higher impurity concentration. On the other hand, the source and drain regions are formed in a lower impurity concentration region. Thereby, the source/drain capacitance of the output MOS transistor may be reduced, and the input/output capacitance of the semiconductor device may be reduced.

Abstract: A semiconductor device is provided in its base region with an emitter region consisting of a p-type first impurity layer having a first impurity concentration peak at a first depth and a p-type second impurity layer having an impurity concentration peak at a second depth, and ohmic contact is provided in the p-type second impurity layer. Due to this structure, the operability of an SRAM memory cell defining an emitter region of a bipolar transistor by a source/drain region of a MOS transistor can be improved.

Abstract: A bipolar transistor is formed by forming a base region continuing from a source/drain region of an MOS transistor, as a link base region, and forming an emitter region at a bit line contact hole by impurity implantation. Alternatively, the bipolar transistor is formed by forming an intrinsic base region and an emitter region at a bit line contact hole by impurity implantation. The intrinsic base region is made deeper than the source/drain region. Further, the impurity of the intrinsic base region is made different from that of the link base region.

Abstract: In a bipolar transistor of a type in which metal electrodes are formed in direct contact with a p-type external base region and an n-type collector region, respectively, an external base region surrounding an outer periphery of an n-type emitter region is formed. A metal electrode is formed on the emitter region with a polycrystalline silicon layer therebetween. Thereby, formation of a buried diffusion layer can be eliminated, and thus a manufacturing cost of the bipolar transistor can be reduced while achieving a high performance of the bipolar transistor.

Abstract: A semiconductor device allowing reduction in collector resistance can be obtained without complicating manufacturing processes. In the semiconductor device, a first impurity layer of a first conductivity type having an impurity concentration higher than that of first semiconductor region is provided such that substantially all the upper portion thereof is in contact with a lower surface of a first element isolation insulating film which is formed between a base layer and a collector extraction layer As a result, the first impurity layer serves as a current path, reducing collector resistance. In addition, the first impurity layer can be easily formed by ion implantation, so that manufacturing processes will not be complicated.

Abstract: The invention provides an SRAM memory cell structure permitting increase of integration density while maintaining operation stability. A memory cell in the SRAM includes a pair of access transistors, a pair of driver transistors, and a pair of load transistors. The gate insulating film of access transistor is formed of a single layer of silicon oxide film, while the gate insulating film of driver transistor is formed of a stacked layer formed of a silicon oxide film and a silicon nitride film. The pair of load transistors are formed of two layers of polycrystalline silicon layers stacked upon each other with an insulating film therebetween. A source region and a drain region are formed in each of polycrystalline silicon layers with each channel region therebetween. One drain region forms a gate opposite to the other channel region, while the other drain region forms a gate opposite to the one channel region.