Patents by Inventor Yukio Suzuki

Yukio Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6018073
    Abstract: Taxane derivatives having an alkoxy, alkenoxy or aryloxy substituted C13 side chain.
    Type: Grant
    Filed: December 17, 1997
    Date of Patent: January 25, 2000
    Assignee: Florida State University
    Inventors: Robert A. Holton, Ki-byung Chai, Hamid Idmoumaz, Hossain Nadizadeh, Kasthuri Rengan, Yukio Suzuki, Chunlin Tao
  • Patent number: 6011056
    Abstract: Taxane derivatives having alternative C9 substituents.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: January 4, 2000
    Assignee: Florida State University
    Inventors: Robert A. Holton, Ki-byung Chai, Yukio Suzuki
  • Patent number: 6008256
    Abstract: A composition for local anesthesia which comprises (A) lidocaine, (B) a catecholamine such as epinephrine in an amount of, for example, 1/200,000 (g/ml) based on the volume of the composition, and (C) one or more amino acids such as glycine, glutamic acid, and L-glutamic acid-L-lysine or one or more hydroxycarboxylic acids such as lactic acid, glycolic acid, and citric acid, which has a duration suitable for short-time dental operations such as tooth extraction and excellent storage stability.
    Type: Grant
    Filed: February 27, 1998
    Date of Patent: December 28, 1999
    Assignee: Showa Yakuhin Kako Co., Ltd.
    Inventors: Mitsuhiro Haraguchi, Kazuhiro Ono, Takashi Osada, Yukio Suzuki
  • Patent number: 6004949
    Abstract: An aqueous pharmaceutical composition comprising sodium cromoglicate as an active ingredient and a quaternary ammonium compound such as benzalkonium chloride as a preservative, characterized in that said composition comprises a precipitation inhibitor selected from the group consisting of alkanolamines including 2-aminoethanol and tocopherols including d-.alpha.-tocopherol is provided. The composition has characteristic feature of free from precipitation or turbidity in manufacturing processes and during storage.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: December 21, 1999
    Assignee: Showa Yakuhin Kako Co., Ltd.
    Inventors: Junko Shima, Kazuhiro Ono, Takashi Osada, Yukio Suzuki
  • Patent number: 5990325
    Abstract: Process for the preparation of a derivative or analog of baccatin III or 10-desacetyl baccatin III having a C9 substituent other than keto in which the C9 keto substituent of taxol, a taxol analog, baccatin III or 10-desacetyl baccatin III is selectively reduced to the corresponding hydroxy group.
    Type: Grant
    Filed: March 5, 1993
    Date of Patent: November 23, 1999
    Assignee: Florida State University
    Inventors: Robert A. Holton, Carmen Somoza, Yukio Suzuki, Mitsuru Shindo
  • Patent number: 5905948
    Abstract: A therefor method of manufacturing tuning circuits for constituting a high frequency channel selecting circuit for a radio receiver. The method can eliminate the complicated coil inductance adjustment for tracking on the circuit board, so that the circuit elements can be arranged freely without any interference between the tuning circuits. The variable capacitance diodes (D1, D2; D3, D4; D5, D6) and fixed capacitances (C1; C4; C7) are classified; a fixed capacitance is selected according to a ranking of capacitance value of the variable capacitance diodes, to obtain a variable capacitance range or a ratio (C.sub.max /C.sub.min) determined for each tuning circuit; and the inductance of a coil (L1; L2; L3) of each tuning circuit is adjusted in such a way that tracking error can be eliminated on the basis of one common tuning voltage, before the tuning circuits are mounted on the circuit board.
    Type: Grant
    Filed: July 25, 1996
    Date of Patent: May 18, 1999
    Assignee: Toko Kabushiki Kaisha
    Inventor: Yukio Suzuki
  • Patent number: 5808934
    Abstract: An EEPROM operable at a reduced power source voltage comprises a decoder circuit for decoding input signals, a memory array for storing the decoded, a reading circuit for operating the decoder circuit and the memory array, and for reading out data stored in the memory array, and a writing circuit for operating the decoder circuit and the memory array, and for writing data to the memory array. The EEPROM is divided into a first circuit area comprising a plurality of first transistors driven by a first power source voltage, an absolute value of a threshold voltage of the first transistors in the first circuit area being within the range of approximately 0.3 V to 0.7 V, the first circuit area including at least the reading circuit, and a second circuit area comprising a plurality of second transistors driven by a second power source voltage, an absolute value of a threshold voltage of the second transistors in the second circuit area being within the range of approximately 0.7 V to 0.
    Type: Grant
    Filed: July 19, 1995
    Date of Patent: September 15, 1998
    Assignee: Seiko Instruments Inc.
    Inventors: Kazuaki Kubo, Yukio Suzuki, Masanori Miyagi
  • Patent number: 5739362
    Abstract: Taxane derivatives having an alkoxy, alkenoxy or aryloxy substituted C13 side chain.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: April 14, 1998
    Assignee: Florida State University
    Inventors: Robert A. Holton, Ki-byung Chai, Hamid Idmoumaz, Hossain Nadizadeh, Kasthuri Rengan, Yukio Suzuki, Chunlin Tao
  • Patent number: 5678212
    Abstract: An electronic tuning circuit for an AM radio receiver in which a signal of a specific frequency is selected from the input signal from an antenna is provided, this tuning circuit having a tuning transformer with a first winding and a second winding, the number of turns on the first winding being greater than the number of turns on said second winding, the input from the antenna being applied to the second winding of the tuning transformer, and further having two varactor diodes, each of which is connected in series with a DC-blocking capacitor, these series-connected varactor-capacitor combinations being connected in parallel with the first winding of the tuning transformer such that the polarities of the varactor diodes are mutually opposing.
    Type: Grant
    Filed: September 11, 1995
    Date of Patent: October 14, 1997
    Assignee: Toko Kabushiki Kaisha
    Inventors: Koichi Sakai, Ken Kasahara, Hajime Yokoyama, Noboru Takada, Yukio Suzuki
  • Patent number: 5666171
    Abstract: An image projector comprises a liquid crystal display module and a light source both contained in a housing. The housing is formed with an inlet and an outlet, and is provided with a fan. An air flow channel is provided between the inlet and the outlet within the housing. There is provided a wind separator in the air flow channel, which separator separates cooling air such that cooling air flows separately towards the liquid crystal display module and the light source, for better cooling effect.
    Type: Grant
    Filed: July 28, 1995
    Date of Patent: September 9, 1997
    Assignee: Casio Computer Co., Ltd.
    Inventors: Hideki Nakamura, Yukio Suzuki
  • Patent number: 5635928
    Abstract: A data processing device including a keyboard with a key; a lid provided to an edge of the keyboard so as to be pivotable from a closed position, to a predetermined angle, and further to an open position; a key support mechanism movable between a first position for supporting the key in an operation condition and a second position wherein the key is not supported; a follower in connection with the key support mechanism so that the follower and the key support move in association; and a driver connected with the lid so as to operate in association with pivotal movement of the lid, the driver driving the follower only when the lid is pivoted between the closed position and the predetermined angle so that the key support mechanism moves from the first position into the second position when the lid is pivoted open between the closed position to the predetermined angle and the key support mechanism remains in the second position when the lid is pivoted open to the predetermined angle or greater.
    Type: Grant
    Filed: December 8, 1995
    Date of Patent: June 3, 1997
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Takeyuki Takagi, Hiroaki Okada, Yoshijiro Yamamoto, Yukio Suzuki
  • Patent number: 5610428
    Abstract: A semiconductor integrated circuit comprises a semiconductor substrate of a first conductivity type, at least one electrically erasable floating gate type semiconductor non-volatile memory transistor disposed on a surface of the semiconductor substrate, a well region of a second conductivity type formed in the surface of the semiconductor substrate, and a program voltage switching transistor of the first conductivity type disposed in the well region. A field insulation film is disposed on the surface of the semiconductor substrate. A field dope region of the first conductivity type is provided beneath the field insulation film. The field dope region preferably has an impurity concentration higher than an impurity concentration of the semiconductor substrate. By this construction, current leakage is prevented at the time when a high voltage occurs such as, for example, when performing a writing operation with respect to EEPROM.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 11, 1997
    Assignee: Seiko Instruments Inc.
    Inventors: Yukio Suzuki, Haruo Konishi, Yoshikazu Kojima
  • Patent number: 5512847
    Abstract: In an input level converter for TTL--CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS--TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.
    Type: Grant
    Filed: October 6, 1994
    Date of Patent: April 30, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Yukio Suzuki, Ikuro Masuda, Masahiro Iwamura, Shinji Kadono, Akira Uragami, Masayoshi Yoshimura, Toshiaki Matsubara
  • Patent number: 5495183
    Abstract: In an input level converter for TTL--CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS--TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.
    Type: Grant
    Filed: May 12, 1995
    Date of Patent: February 27, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Yukio Suzuki, Ikuro Masuda, Masahiro Iwamura, Shinji Kadono, Akira Urragami, Masayoshi Yoshimura, Toshiaki Matsubara
  • Patent number: 5492593
    Abstract: A parts feeder for feeding parts that are disposed on a carrier having a base tape and an adhesive tape. Parts are disposed above holes which are formed at equal intervals on the base tape, and the parts are held by an adhesive tape adhered to a lower surface of the base tape. The feeder includes a pitched feeding mechanism for intermittently feeding the carrier tape at a predetermined pitch, a separating mechanism for separating the adhesive tape from the base tape in synchronization with the feeding of the carrier tape at an adhesive tape separating stage, and a pressing mechanism for pressing the parts disposed on the base tape against the base tape prior to the separation of the adhesive tape from the base tape at the adhesive tape separating stage.
    Type: Grant
    Filed: June 17, 1994
    Date of Patent: February 20, 1996
    Assignees: Asahi Kogaku Kabushiki Kaisha, Kabushiki Kaisha Toshiba, Japan Tobacco Inc., Asahi Kohki Co., Ltd.
    Inventors: Naotugu Ariga, Yukio Suzuki, Saburo Ogawa, Etuo Minamihama, Takayuki Akatsuka
  • Patent number: 5371713
    Abstract: In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.
    Type: Grant
    Filed: March 9, 1994
    Date of Patent: December 6, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Katsumi Ogiue, Yukio Suzuki, Ikuro Masuda, Masanori Odaka, Hideaki Uchida
  • Patent number: 5360965
    Abstract: A microwave oven includes a heating chamber, a plurality of cooking utensils detachably disposed in the heating chamber selectively in accordance with the cooking contents, a plurality of heat sources heating food placed on or contained in the cooking utensil and including a magnetron, an oven heater and a grill heater, optical sensors determining the cooking utensil disposed in the heating chamber, and a microcomputer. The cooking utensils include a glass dish, thawing gridiron, pot, upper and lower top plates, one-legged top plate, and gridiron. A microwave cooking mode is selected when the determination of the optical sensors indicates that neither upper nor lower top plate is present in the heating chamber. A heater cooking mode is selected when either upper or top plate is present. When the heater cooking mode is selected on the basis of presence of the upper top plate, either an oven mode or a grill mode is selected depending upon presence or absence of the gridiron.
    Type: Grant
    Filed: March 9, 1993
    Date of Patent: November 1, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazunori Ishii, Hisao Kano, Nobuichi Nishimura, Masayuki Aoki, Yukio Suzuki, Takamichi Sujaku, Yoshio Okamura, Masahiko Wada, Takumi Ohno, Ryuho Narita
  • Patent number: 5317095
    Abstract: An .alpha.-D-hlycosyl kasugamycin having the formula (III): ##STR1## wherein n is an integer of not less than 1. According to the present invention, the novel substance which is highly safe and easily hydrolyzed with .alpha.-glucosidase to exhibit physiological activities inherent to kasugamycin is obtained.
    Type: Grant
    Filed: March 3, 1993
    Date of Patent: May 31, 1994
    Assignee: Hayashibara Biochemical Laboratories, Inc.
    Inventors: Yukio Suzuki, Koutarou Muroyama, Kei Suzuki
  • Patent number: 5311482
    Abstract: In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.
    Type: Grant
    Filed: July 16, 1993
    Date of Patent: May 10, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Katsumi Ogiue, Yukio Suzuki, Ikuro Masuda, Masanori Odaka, Hideaki Uchida
  • Patent number: 5245224
    Abstract: In an input level converter for TTL-CMOS level conversion (or other conversion to CMOS) for an internal logic block operating with CMOS levels, an output transistor for executing the charge or discharge of the output capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the input level converter can be lessened. Similarly, in an output level converter for CMOS-TTL level conversion (or other conversion from CMOS) for the internal logic block operating with the CMOS levels, an output transistor for executing the charge or discharge of the output load capacitance thereof is formed of a bipolar transistor. Thus, the propagation delay times and their capacitance-dependencies of the output level converter can also be lessened.
    Type: Grant
    Filed: March 3, 1992
    Date of Patent: September 14, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Yukio Suzuki, Ikuro Masuda, Masahiro Iwamura, Shinji Kadono, Akira Uragami, Masayoshi Yoshimura, Toshiaki Matsubara