Patents by Inventor Yukio Terasaki

Yukio Terasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220309339
    Abstract: An information processing device includes a reservoir layer, and a read-out layer. The reservoir layer includes a plurality of nodes that generate a feature space including information of an input signal input to the reservoir layer, the read-out layer performs an operation of applying a connection weight to each of signals sent from the reservoir layer, and the number of signals sent to the read-out layer from the reservoir layer is smaller than the number of the plurality of nodes.
    Type: Application
    Filed: October 8, 2021
    Publication date: September 29, 2022
    Applicant: TDK CORPORATION
    Inventors: Yukio TERASAKI, Kazuki NAKADA
  • Publication number: 20220261559
    Abstract: An arithmetic circuit includes a variable resistance element having three terminals of a first terminal, a second terminal, and a third terminal and configured such that the resistance value is variable, an input line connected to the first terminal, a capacitor connected to the second terminal and provided between the second terminal and the reference potential, a first switching element connected to the third terminal, a wiring connected to the third terminal through the first switching element, a second switching element connected to a first end of the wiring, and a third switching element connected to a second end of the wiring.
    Type: Application
    Filed: February 27, 2020
    Publication date: August 18, 2022
    Applicant: TDK CORPORATION
    Inventors: Tatsuo SHIBATA, Yukio TERASAKI
  • Patent number: 11340869
    Abstract: A sum-of-products operator including: a first circuit configured to generate a plurality of signals, each of which corresponds to each of a plurality of data; a second circuit including a first operation circuit configured to multiply each of the signals generated by the first circuit by a weight using a plurality of variable resistive elements having variable resistance values, and to calculate a sum of a plurality of results of multiplications; a third circuit configured to calculate a result of summing values corresponding to the data or a result of the summing value after being adjusted; and a fourth circuit including a differential circuit configured to output a difference between a calculated result in the first operation circuit of the second circuit and a calculated result in the third circuit.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: May 24, 2022
    Assignee: TDK CORPORATION
    Inventor: Yukio Terasaki
  • Patent number: 11335849
    Abstract: A magnetic domain wall displacement type magnetic recording element which comprises: a first magnetization fixed part which is stacked in a first direction, a magnetic recording layer which includes a magnetic domain wall and extends in a second direction which crosses with the first direction, a non-magnetic layer which is provided between the first magnetization fixed part and the magnetic recording layer, and a first via part which is electrically connected to the magnetic recording layer, wherein at least a part of the first via part is located at a position which is apart from the first magnetization fixed part in the second direction in planar view observed from the first direction, the magnetic recording layer includes a first part which has a position where the first magnetization fixed part overlaps with the magnetic recording layer in planar view observed from the first direction, and a width of the first via part in a third direction which is orthogonal to the second direction is larger than a widt
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: May 17, 2022
    Assignee: TDK CORPORATION
    Inventors: Shogo Yamada, Tomoyuki Sasaki, Yukio Terasaki, Tatsuo Shibata
  • Publication number: 20220138441
    Abstract: A multiply and accumulate calculation device including a variable resistor array unit having a plurality of variable resistance elements, a reference array unit having a reference resistance element having a fixed resistance value, a signal input unit that generates an input signal from input data, and inputs the input signal to the variable and reference resistance elements, a first detection unit that detects a current flowing through the variable resistor array unit, based on the input signal applied to the variable resistance elements, a second detection unit that detects a current flowing through the reference array unit, based on the input signal applied to the reference resistance element, and a correction calculation unit that performs a predetermined calculation on the output from the first detection unit, based on the output from the second.
    Type: Application
    Filed: March 1, 2019
    Publication date: May 5, 2022
    Applicant: TDK CORPORATION
    Inventors: Tatsuo SHIBATA, Yukio TERASAKI
  • Publication number: 20220130900
    Abstract: An arithmetic operation circuit including: a variable resistance element that includes three terminals that are a first terminal, a second terminal, and a third terminal and is configured to be able to change a resistance value; a first electrode connected to the first terminal; a second electrode; a third electrode; a first switching element connected between the second electrode and the second terminal; a second switching element connected between the third electrode and the third terminal; and a capacitor connected between a transmission line connecting the second terminal and the first switching element and the ground.
    Type: Application
    Filed: February 27, 2020
    Publication date: April 28, 2022
    Applicant: TDK CORPORATION
    Inventor: Yukio TERASAKI
  • Publication number: 20220092396
    Abstract: A product-sum operation device including: product operation units generating output signals by multiplying input signals corresponding to input values; a current detection unit executing a current detecting process in which a current output from the product operation units with a predetermined time delay from input of the input signal and a current output from the product operation units at an interval thereafter are detected in a time span from a first transient response to before occurrence of a second transient response, the first transient response due to charging to a parasitic capacitance of the product operation units by input of the input signal and the second transient response being due to discharging from the parasitic capacitance of the product operation units by input of the input signal; and a sum operation unit calculating a value relating to a total sum of the output signals based on currents detected.
    Type: Application
    Filed: January 9, 2019
    Publication date: March 24, 2022
    Applicant: TDK CORPORATION
    Inventors: Kuniyasu ITO, Tatsuo SHIBATA, Yukio TERASAKI
  • Publication number: 20210312272
    Abstract: A control device of an array including neuromorphic elements that multiply a signal by a weight corresponding to a value of a variable characteristic is provided with a control unit which calculates update amounts of element conductances in a neuromorphic array on the basis of weight update amounts from a learning algorithm, and, after applying a write signal for changing conductances in the neuromorphic array, selects certain elements with reference to a predetermined threshold value and applies an additional write signal.
    Type: Application
    Filed: December 20, 2018
    Publication date: October 7, 2021
    Applicant: TDK CORPORATION
    Inventor: Yukio TERASAKI
  • Publication number: 20200293889
    Abstract: A neural network device includes a decimation unit configured to convert a discrete value of an input signal to a discrete value having a smaller step number than a quantization step number of the input signal on the basis of a predetermined threshold value to generate a decimation signal a modulation unit configured to modulate a discrete value of the decimation signal generated by the decimation unit to generate a modulation signal indicating the discrete value of the decimation signal, and a weighting unit including a neuromorphic element configured to output a weighted signal obtained by weighting the modulation signal through multiplication of the modulation signal generated by the modulation unit by a weight according to a value of a variable characteristic.
    Type: Application
    Filed: March 23, 2020
    Publication date: September 17, 2020
    Applicant: TDK CORPORATION
    Inventor: Yukio TERASAKI
  • Publication number: 20200272891
    Abstract: A controller is a controller of an array including a neuromorphic element that multiplies a weight based on a value of a variable characteristic by a signal, and includes a control unit that controls the characteristic of the neuromorphic element by using a discretization step size obtained so that a predetermined condition for reducing an error or a predetermined condition for improving accuracy is satisfied on the basis of a case where a true value of the weight obtained with a higher accuracy than a resolution of the characteristic of the neuromorphic element is used and a case where a discretization step size which is set for the characteristic of the neuromorphic element is used.
    Type: Application
    Filed: February 19, 2018
    Publication date: August 27, 2020
    Applicant: TDK CORPORATION
    Inventor: Yukio TERASAKI
  • Publication number: 20200210818
    Abstract: An array device includes: a first array area that includes a neuromorphic element which is configured to multiply a signal by a weight corresponding to a variable characteristic value and outputs a first signal which is a result of processing an input signal using the neuromorphic element; and a retention unit that is able to retain the first signal output from the first array area or a second signal which is output when the first signal is input to a predetermined computing unit and is configured to input the retained first signal or the retained second signal to the first array area.
    Type: Application
    Filed: August 3, 2018
    Publication date: July 2, 2020
    Applicant: TDK CORPORATION
    Inventor: Yukio TERASAKI
  • Publication number: 20200150927
    Abstract: A sum-of-products operator including: a first circuit configured to generate a plurality of signals, each of which corresponds to each of a plurality of data; a second circuit including a first operation circuit configured to multiply each of the signals generated by the first circuit by a weight using a plurality of variable resistive elements having variable resistance values, and to calculate a sum of a plurality of results of multiplications; a third circuit configured to calculate a result of summing values corresponding to the data or a result of the summing value after being adjusted; and a fourth circuit including a differential circuit configured to output a difference between a calculated result in the first operation circuit of the second circuit and a calculated result in the third circuit.
    Type: Application
    Filed: November 6, 2019
    Publication date: May 14, 2020
    Applicant: TDK CORPORATION
    Inventor: Yukio TERASAKI
  • Publication number: 20200044141
    Abstract: A magnetic domain wall displacement type magnetic recording element which comprises: a first magnetization fixed part which is stacked in a first direction, a magnetic recording layer which includes a magnetic domain wall and extends in a second direction which crosses with the first direction, a non-magnetic layer which is provided between the first magnetization fixed part and the magnetic recording layer, and a first via part which is electrically connected to the magnetic recording layer, wherein at least a part of the first via part is located at a position which is apart from the first magnetization fixed part in the second direction in planar view observed from the first direction, the magnetic recording layer includes a first part which has a position where the first magnetization fixed part overlaps with the magnetic recording layer in planar view observed from the first direction, and a width of the first via part in a third direction which is orthogonal to the second direction is larger than a widt
    Type: Application
    Filed: November 15, 2018
    Publication date: February 6, 2020
    Applicant: TDK CORPORATION
    Inventors: Shogo YAMADA, Tomoyuki SASAKI, Yukio TERASAKI, Tatsuo SHIBATA
  • Patent number: 8219742
    Abstract: The memory controller comprises a data holding unit which is composed of plural unit areas each for holding data corresponding to one logical page among logical pages each composed of plural logical sectors each assigned a logical address provided from a host system. The memory controller writes data held in a unit area which holds large amounts of write data, to the flash memories, in preference to data held in a unit area which holds small amounts of write data.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: July 10, 2012
    Assignee: TDk Corporation
    Inventor: Yukio Terasaki
  • Patent number: 8200890
    Abstract: First operations and second operations are performed in parallel. The first operations are operations to write first data to a first unit area which is any one of unit areas. The second operations are operations to read second data corresponding to the same logical page as first data from one or more flash memories and write the second data to a second unit area which is any one of the unit areas and different from the first unit area. Data transfer is performed between the first unit area and the second unit area so as to form data composed of the first data and a portion of the second data which is not replaced with the first data.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: June 12, 2012
    Assignee: TDK Corporation
    Inventors: Yukio Terasaki, Takeshi Kamono
  • Publication number: 20100095054
    Abstract: The memory controller comprises a data holding unit which is composed of plural unit areas each for holding data corresponding to one logical page among logical pages each composed of plural logical sectors each assigned a logical address provided from a host system. The memory controller writes data held in a unit area which holds large amounts of write data, to the flash memories, in preference to data held in a unit area which holds small amounts of write data.
    Type: Application
    Filed: October 13, 2009
    Publication date: April 15, 2010
    Applicant: TDK Corporation
    Inventor: Yukio Terasaki
  • Publication number: 20100082889
    Abstract: First operations and second operations are performed in parallel. The first operations are operations to write first data to a first unit area which is any one of unit areas. The second operations are operations to read second data corresponding to the same logical page as first data from one or more flash memories and write the second data to a second unit area which is any one of the unit areas and different from the first unit area. Data transfer is performed between the first unit area and the second unit area so as to form data composed of the first data and a portion of the second data which is not replaced with the first data.
    Type: Application
    Filed: September 29, 2009
    Publication date: April 1, 2010
    Applicant: TDK Corporation
    Inventors: Yukio Terasaki, Takeshi Kamono
  • Patent number: 7617352
    Abstract: A memory controller includes decision means responsive to a request to write user data issued by a host computer for determining whether progressive data writing for writing user data to a target page designated by a host address is possible, and write means responsive to an affirmative determination by the decision means for writing user data to the target page without performing an inter-block data transfer. Thus, a series of data write operations for completing data writing can be performed at high speed because the frequency of inter-block data transfers is low.
    Type: Grant
    Filed: December 26, 2001
    Date of Patent: November 10, 2009
    Assignee: TDK Corporation
    Inventors: Naoki Mukaida, Kenzo Kita, Yukio Terasaki
  • Patent number: 7606993
    Abstract: A controller included in a flash memory system, which can be applied to a memory interface of a host computer is disclosed. A buffer is used for data exchange operation between the host computer and the controller, and data exchange operation between a flash memory and the controller. A host interface control block as a first control block controls data exchange operation between the buffer and the host computer. A flash sequencer block as a second control block controls data exchange operation between the buffer and the flash memory. The host interface control block controls input and output operation of the buffer, based on a memory control signal and a memory address signal supplied from the host computer. The flash sequencer block controls input and output operation of the buffer at a one-page size of the flash memory.
    Type: Grant
    Filed: March 4, 2004
    Date of Patent: October 20, 2009
    Assignee: TDK Corporation
    Inventors: Tsuyoshi Oyaizu, Yukio Terasaki
  • Patent number: 7020739
    Abstract: An object of the present invention is to provide a memory controller that can perform a series of data write operations so as to complete the data writing at high speed. A memory controller includes means for dividing the physical blocks into a plurality of groups, means for forming a plurality of virtual blocks by virtually combining a plurality of physical blocks each of which belongs to a different group, and means for assigning adjacent host addresses to different physical blocks belonging to the same virtual block. Thus, when a host computer issues a request to access the plurality of successive host addresses, the physical blocks to be accessed are different physical blocks. Since the physical blocks to be accessed can therefore operate independently, a series of operations can be performed in parallel.
    Type: Grant
    Filed: December 5, 2001
    Date of Patent: March 28, 2006
    Assignee: TDK Corporation
    Inventors: Naoki Mukaida, Kenzo Kita, Yukio Terasaki